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Verilog design in Cadence

kenambo

 Hi,

 Is there anyway that i can design a digital circuit in Virtuoso Schematic window...

And include the *.v file in the schematic capture window..

 

Thanks...

Parents

  • Sali said:
    module VCCS(p,n,pc,nc);
    inout p,n;
    electrical p,n,pc,nc;
    parameter real gain=1;
    branch (p,n) iSrc;
    analog begin
    I(iSrc) <+ gain*V(pc,nc);
    end
    endmodulet pc,nc;

    Not sure why you posted this on the end of another thread, but the code you posted has typos in it - it wouldn't even syntax compile. I used a command-line example to try this out (having fixed the typos):

    `include "disciplines.vams"

    module VCCS(p,n,pc,nc);
    inout p,n;
    input pc,nc;
    electrical p,n,pc,nc;
    parameter real gain=1;
    branch (p,n) iSrc;
    analog begin
    I(iSrc) <+gain*V(pc,nc);
    end
    endmodule

    module test;
    electrical gnda;
    ground gnda;

    vsource #(.freq(1M),.ampl(0.5), .type("sine")) V1(n1,gnda);
    resistor #(.r(1k)) R1(op1,gnda);
    VCCS #(.gain(1m)) I1(op1,gnda,n1,gnda);

    endmodule

    And this together with testVCCS.scs :

    tran tran stop=2u

    I then ran "irun -gui testVCCS.scs testVCCS.vams" and I see these results (having problems uploading the picture, so I'll try again in a moment). Looks pretty OK to me.

    Andrew.

     

     


    input pc,nc;
Reply

  • Sali said:
    module VCCS(p,n,pc,nc);
    inout p,n;
    electrical p,n,pc,nc;
    parameter real gain=1;
    branch (p,n) iSrc;
    analog begin
    I(iSrc) <+ gain*V(pc,nc);
    end
    endmodulet pc,nc;

    Not sure why you posted this on the end of another thread, but the code you posted has typos in it - it wouldn't even syntax compile. I used a command-line example to try this out (having fixed the typos):

    `include "disciplines.vams"

    module VCCS(p,n,pc,nc);
    inout p,n;
    input pc,nc;
    electrical p,n,pc,nc;
    parameter real gain=1;
    branch (p,n) iSrc;
    analog begin
    I(iSrc) <+gain*V(pc,nc);
    end
    endmodule

    module test;
    electrical gnda;
    ground gnda;

    vsource #(.freq(1M),.ampl(0.5), .type("sine")) V1(n1,gnda);
    resistor #(.r(1k)) R1(op1,gnda);
    VCCS #(.gain(1m)) I1(op1,gnda,n1,gnda);

    endmodule

    And this together with testVCCS.scs :

    tran tran stop=2u

    I then ran "irun -gui testVCCS.scs testVCCS.vams" and I see these results (having problems uploading the picture, so I'll try again in a moment). Looks pretty OK to me.

    Andrew.

     

     


    input pc,nc;
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