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Verilog design in Cadence

kenambo over 11 years ago

Hi,

Is there anyway that i can design a digital circuit in Virtuoso Schematic window...

And include the *.v file in the schematic capture window..

Thanks...

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Sali over 11 years ago

Thank you so much Andrew, and sorry for being late in my reply I had a problem accessing my cadence account ant it solved now. Thank you again, Sali
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Sali over 11 years ago

Thank you so much Andrew, and sorry for being late in my reply I had a problem accessing my cadence account ant it solved now. Thank you again, Sali
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