Accuracy of CROSS() function in Verilog-A

I had some trouble running it - I had to change KT to be a smaller number (see the comment in the code below). The key seemed to be moving the definition of phase to above the cross. I think the issue is that it was using the previous iteration's value of phase.

I also changed it to use phase again rather than V(phase_out) (spectre advised me that it had changed it back to a real number for performance reasons anyway).

This was the netlist I used to test it with:

 //

OSC1 (in op1 op2) DCO

v1 (in 0) vsource type=dc dc=1
r1 (op1 0) resistor r=100k
r2 (op2 0) resistor r=100k

ahdl_include "DCO.va"

tran tran stop=1m

 // VerilogA for VERILOG_A_MODEL, DCO, veriloga

`include "constants.vams"
`include "disciplines.vams"

module DCO (in, out,out1);

input in;
output out,out1;
electrical in, out,out1;
parameter real Vlo=0, Vhi=1.25;

parameter real Vth=0;

parameter real ttol=1p;
parameter real vtol=1p;
parameter real tt = 1p;


// changed KT value because it seemed enormous to me otherwise!
parameter real KT=200e-6;
parameter real Tv_0= 0.5n;
real n,delay;
parameter real start_delay=1n;

real T_period;
real Time_Span;
real phase,reset;



analog begin

@(initial_step) begin
      V(out) <+ 0;    
      
      delay= start_delay;
      reset =0;
 end
 
 T_period = Tv_0 + KT * V(in) ;

// $strobe("T_period is ",T_period);
 
 

 phase= idt(1,0,reset) - delay; // Phase Integration
 reset =0;

// V(phase_out) <+ phase;
    
 @(cross(phase-T_period,+1,ttol,vtol)) begin
       reset=1;
       delay =0;
       $strobe("T_period is ",T_period);
       $strobe("cross val is ",phase-T_period);
       $strobe("EDGE_TIME = %rs \n", $abstime);
      
     end
     
// $strobe("phase is ",phase);


  n= (phase >=0) && (phase < (T_period/2));
     
     V(out) <+ transition(n ? Vhi:Vlo,0,tt);
     V(out1) <+ phase ;
     
     //$bound_step(0.01n);     
     
end
 endmodule

I had some trouble running it - I had to change KT to be a smaller number (see the comment in the code below). The key seemed to be moving the definition of phase to above the cross. I think the issue is that it was using the previous iteration's value of phase.

I also changed it to use phase again rather than V(phase_out) (spectre advised me that it had changed it back to a real number for performance reasons anyway).

This was the netlist I used to test it with:

 //

OSC1 (in op1 op2) DCO

v1 (in 0) vsource type=dc dc=1
r1 (op1 0) resistor r=100k
r2 (op2 0) resistor r=100k

ahdl_include "DCO.va"

tran tran stop=1m

 // VerilogA for VERILOG_A_MODEL, DCO, veriloga

`include "constants.vams"
`include "disciplines.vams"

module DCO (in, out,out1);

input in;
output out,out1;
electrical in, out,out1;
parameter real Vlo=0, Vhi=1.25;

parameter real Vth=0;

parameter real ttol=1p;
parameter real vtol=1p;
parameter real tt = 1p;


// changed KT value because it seemed enormous to me otherwise!
parameter real KT=200e-6;
parameter real Tv_0= 0.5n;
real n,delay;
parameter real start_delay=1n;

real T_period;
real Time_Span;
real phase,reset;



analog begin

@(initial_step) begin
      V(out) <+ 0;    
      
      delay= start_delay;
      reset =0;
 end
 
 T_period = Tv_0 + KT * V(in) ;

// $strobe("T_period is ",T_period);
 
 

 phase= idt(1,0,reset) - delay; // Phase Integration
 reset =0;

// V(phase_out) <+ phase;
    
 @(cross(phase-T_period,+1,ttol,vtol)) begin
       reset=1;
       delay =0;
       $strobe("T_period is ",T_period);
       $strobe("cross val is ",phase-T_period);
       $strobe("EDGE_TIME = %rs \n", $abstime);
      
     end
     
// $strobe("phase is ",phase);


  n= (phase >=0) && (phase < (T_period/2));
     
     V(out) <+ transition(n ? Vhi:Vlo,0,tt);
     V(out1) <+ phase ;
     
     //$bound_step(0.01n);     
     
end
 endmodule