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  3. Accuracy of CROSS() function in Verilog-A

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Accuracy of CROSS() function in Verilog-A

RFStuff
RFStuff over 11 years ago

Dear All,

I am using cross() in verilog-A as below:-

 

vtol=1e-12;

@(cross(phase-10u,+1,ttol,vtol)) begin
       $strobe("TIME = %rs \n", $abstime);
     end

But when I checked the abstime, it is NOT exactly at 10u of phase but at 10.541u of phase. This error is much larger than my vtol value.

But when I chnaged to strobeperiod of tran analysis to  1ns, abstime shows up at phase value of 10.002u.

I wonder why such descrpancy and why vtol  is NOT playing any role here.

Kind Regards,

 

 

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  • Andrew Beckett
    Andrew Beckett over 11 years ago

    My guess is that this might be something to do with now phase is defined. So can you show the rest of the code (at least the part that is setting the phase variable?).

    Also, what is ttol set to?

    And what version of spectre are you using?

    Regards,

    Andrew.

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  • RFStuff
    RFStuff over 11 years ago

    Dear Andrew,

    I am using Spectre version :-  sub-version  12.1.0.402.isr5.

    The code is a simple one which model a digital Oscillator whose Time period varies with respect to the input voltage V(in).

    The code is as below:-

     // VerilogA for VERILOG_A_MODEL, DCO, veriloga

    `include "constants.vams"
    `include "disciplines.vams"

    module DCO (in, out,out1);

    input in;
    output out,out1;
    electrical in, out,out1,phase_out;
    parameter real Vlo=0, Vhi=1.25;

    parameter real Vth=0;

    parameter real ttol=1p;
    parameter real vtol=1p;
    parameter real tt = 1p;


    parameter real KT=200e6;
    parameter real Tv_0= 0.5n;
    real n,delay;
    parameter real start_delay=1n;

    real T_period;
    real Time_Span;
    real phase,reset;



    analog begin

    @(initial_step) begin
          V(out) <+ 0;    
          
          delay= start_delay;
     end
     reset =0;
     
     T_period = Tv_0 + KT * V(in) ;
     
     

     V(phase_out) <+ phase;
        
     @(cross(V(phase_out)-T_

    period,+1,ttol,vtol)) begin
           reset=1;
           delay =0;
           $strobe("EDGE_TIME = %rs \n", $abstime);
          
         end
         
          phase= idt(1,0,reset) - delay; // Phase Integration


      n= (phase >=0) && (phase < (T_period/2));
         
         V(out) <+ transition(n ? Vhi:Vlo,0,tt);
         V(out1) <+ phase ;
         
         //$bound_step(0.01n);     
         
    end
     endmodule
     
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  • Andrew Beckett
    Andrew Beckett over 11 years ago

    I had some trouble running it - I had to change KT to be a smaller number (see the comment in the code below). The key seemed to be moving the definition of phase to above the cross. I think the issue is that it was using the previous iteration's value of phase.

    I also changed it to use phase again rather than V(phase_out) (spectre advised me that it had changed it back to a real number for performance reasons anyway).

    This was the netlist I used to test it with:

     //

    OSC1 (in op1 op2) DCO

    v1 (in 0) vsource type=dc dc=1
    r1 (op1 0) resistor r=100k
    r2 (op2 0) resistor r=100k

    ahdl_include "DCO.va"

    tran tran stop=1m


     // VerilogA for VERILOG_A_MODEL, DCO, veriloga
    
    `include "constants.vams"
    `include "disciplines.vams"
    
    module DCO (in, out,out1);
    
    input in;
    output out,out1;
    electrical in, out,out1;
    parameter real Vlo=0, Vhi=1.25;
    
    parameter real Vth=0;
    
    parameter real ttol=1p;
    parameter real vtol=1p;
    parameter real tt = 1p;
    
    
    // changed KT value because it seemed enormous to me otherwise!
    parameter real KT=200e-6;
    parameter real Tv_0= 0.5n;
    real n,delay;
    parameter real start_delay=1n;
    
    real T_period;
    real Time_Span;
    real phase,reset;
    
    
    
    analog begin
    
    @(initial_step) begin
          V(out) <+ 0;    
          
          delay= start_delay;
          reset =0;
     end
     
     T_period = Tv_0 + KT * V(in) ;
    
    // $strobe("T_period is ",T_period);
     
     
    
     phase= idt(1,0,reset) - delay; // Phase Integration
     reset =0;
    
    // V(phase_out) <+ phase;
        
     @(cross(phase-T_period,+1,ttol,vtol)) begin
           reset=1;
           delay =0;
           $strobe("T_period is ",T_period);
           $strobe("cross val is ",phase-T_period);
           $strobe("EDGE_TIME = %rs \n", $abstime);
          
         end
         
    // $strobe("phase is ",phase);
    
    
      n= (phase >=0) && (phase < (T_period/2));
         
         V(out) <+ transition(n ? Vhi:Vlo,0,tt);
         V(out1) <+ phase ;
         
         //$bound_step(0.01n);     
         
    end
     endmodule

     

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  • RFStuff
    RFStuff over 11 years ago

    Dear Andrew,

    Thanks a lot for your time and reply.

    I realised that it is NOT the cross() issue.

    The issue lies in idt(). 

    When the "phase" crosses "T_period" ( cross() is accurate no doubt ) , "reset" becomes one 1 at that instant.

    But idt() becomes zero in the next time point which is NOT controlled one ( it depends upon Spectre simulation).

    This leads to period error of the Oscillator.

    Same is the case for idtmod(). 

    Is there any way I can make idt() = 0 at the exact time instant when "reset" becomes 1 though it is completely abrupt and discontinuous.

     

    Kind Regards,

     

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  • Andrew Beckett
    Andrew Beckett over 11 years ago

    The conventional way of handling this would be to convert the input voltage to the expected instantaneous frequency, and then integrate that to produce the phase. In this example:

           inst_freq = center_freq + vco_gain * V(vin);
          $bound_step (1.0 / (steps_per_period*inst_freq));

          phase = idtmod(inst_freq,0,1);
          V(vout) <+ amp * sin (2 * `PI * phase);

    The phase will ramp up from 0 to 1 and the automatically reset. In this case we're using a sin() to produce a sinusoidal output, but you could also use an @cross or similar to produce a logic output.

    Regards,

    Andrew.

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  • atulkumar245
    atulkumar245 over 3 years ago in reply to Andrew Beckett

    real iout,vd,temp;

    analog initial
    state = 0 ;


    analog begin
    //temp=0;

    vd=V(vc,out);
    @(cross(vd-3,1))
    state=1 ;
    @(cross(vd-2,-1))
    state=0 ;

    $strobe("Vds=%e",vd);

    if (state==1)
    begin
    temp=0.5+0.5*tanh((vd-2)/0.01);
    iout = temp*(vd/500)+(1-temp)*(vd/7000);
    end
    else
    begin
    temp=0.5+0.5*tanh((vd-3)/0.01);
    iout = temp*(vd/500)+(1-temp)*(vd/7000);
    end


    I(vc,out) <+ iout ;
    end

    endmodule

    I want to implement a hysteresis loop in I_V_characteristics at V=3 and V=4 being transition points. Is there any alternative to cross-function? Please help me out in this 

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  • Andrew Beckett
    Andrew Beckett over 3 years ago in reply to atulkumar245

    Why do you need an alternative to the cross function? Surely that does what you want? (the code above appears to have transitions at 3V and 2V).

    Andrew.

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  • atulkumar245
    atulkumar245 over 3 years ago in reply to Andrew Beckett

    Actually, I have to implement a hysteresis with the transition happening at 2 and 3 V . The circuit made with this device used should oscillate but this implementation is showing an error. So I thought maybe it is due to cross so I asked for an alternative.

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