techfile contain section (for example)
electricalRules( characterizationRules( ( areaCap metal1 1.4e-4 ) ( edgeCap metal1 4.0e-5 ) ( sheetRes metal1 0.040000 ))
How to calculate areaCap?
I want to know the method for calculating the parameter "areaCap".
Are you aware that this represents the area capacitance coefficient, so when you know the area you just multiply by this coefficient in order to work out the capacitance? The capacitance can be derived from the permittivity, area and separation distance by a formula - so the coefficient is based on the dielectric material and the plate separation to give a coefficient that you can multiply by the plate area.
The fab or foundry will have derived and measured such coefficients, and they provide the information in the technology file.Hopefully this helps you? You question is pretty vague, so if this does not help, provide more details.
I know this formula. This formula is a flat capacitor.
А flat capacitor contains two electrodes.
( areaCap metal1 1.4e-4 )
1 electrode - metal1
2 electrode - ?
This formula is valid if the relative dielectric constant
of the medium between the electrodes - is constant.How to calculate the capacitance of the structure:
metal1 -- silicon oxide- - silicon nitride -- metal2, etc?
How fab foundry have derived and measured such coefficient (areaCap)?
Such simplistic capacitance measurements are rarely used these days of many layers of metal; the areaCap (areaCapacitance in OA versions of the tools) is the area coefficient of the wire-to-ground (i.e. substrate) capacitance. This is covered in the documentation.
As to how they come up with the value - it's probably either computed using a very simple computation of the dielectric thickness between the substrate and the metal layer in question (the thicknesses of oxides and metals are reasonably well controlled) and the permittivity - see any text which describes capacitance - or maybe they measure it from a test chip. Neither would be hard.
Most reasonable extraction strategies these days would involve using a description of the process stack (thicknesses of conductors, dielectric thicknesses, permittivity of each dielectric, typical widths and spacings) and then using a 3D solver either directly (not good for large number of shapes) or to produce pattern matching models in a variety of different scenarios to allow rapid 2.5D extraction of routing including multi-layer area and fringing effects (and others). So a simplistic single area capitance is of very limited use or accuracy.