Stats

  • Locked Locked
  • Replies 14
  • Subscribers 125
  • Views 22798
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

LVS on a layout imported from Encounter versus the Physical Verilog netlist

Kabal

 

 

I have successfully imported the layout from Encounter, and solved out the residual DRC errors, however; I am not sure now how to do LVS.

Before I had some problems with import which were covered in another subforums here and topics but I solved them all, right now I want to concentrate just on a specific LVS on Encounter Imported Layout issue. 

 

Here are my actions:

 

1) get the verilog design synthesized properly and routed without geometry/connectivity violations in Encounter [DONE] 

 

2) Properly export it to GDS file [DONE] 

 

3) do saveNetlist -phys -includePowerGround from the Encounter, it basically produces a Physical Verilog netlist, which includes cell description + Power pins. [DONE]

 

4) Go to Cadence Virtuoso, do CIW->Import->Verilog, there I point to the physical verilog netlist produced by  Encounter and also point to the newly created library based on technology kit with imported proper metal layers.

 

5) then i start the process of importing scehmatics for CDL, I see that the cells are created one after another, and the main big schematics is created, where each module of the schematic is the standard library cell. However, when I click and get inside that cell I see only ports, and no transistors.

 

It might look OK, since afterall it has imported physical VERILOG netlist, not a transistor schematic.

But problem starts when I try to produce CDL netlist using the IBM provided Perl script for the LVS. The final output of that script is MY_INSTANCE_NAME.netlist.lvs

 

However, when I start now doing LVS on the corrected/DRCed Layout, I get errors like:

a) nMOS on layout is unbound to any schematic device

b) pMOS on Layout is unbound to any schematic device

c) subC on Layout unbound to schematic device

 

Error (c) is OK, I can fix it simbly by adding the substrate contact in the imported schematics. 

(reason for that  is that DRC does not pass without proper amount of substrate contacts on a layout, so in an imported layout I added them.. but then again, I added it also in the schematic, so error (c) was gone)

 

However, what really weird is: why do errors (a) and (b) exist?

 

From one side, I understand, it does not SEE the transistors because the cells imported from physical verilog dont have one (because verilog describes hardware flow not transistor interconnect)

 

But from another side, why would it even try to find transistors?

 

Why does not it treat my imported layout cells as a standalone modules with just ports, because that is what they are.

 

I even tried creating CDL netlist in "Digital" format from the imported schematics view, same thing.

 

Am I missing something trivial here? 

 

Any ideas?


Parents

  • >Kabal, Is the layout view provided by your founder? 

    Yes. They provide GDS file, which I independently imported to my library, and could see all the layouts and open them in layout editor. And during GDS export from Encounter, I merged the final GDS of my design with the GDS file of the standard cells. That is how I had to do it for all the layers to show up correctly.

    >Did you check your layer map file and your rule deck? 

    During that export process I pointed to the MAP file provided by customer as well, that MAP file was specifically made for Soc2GDs transition. Rule deck? whats that? You mean LEF? yes they were provided to Encounter

     >Can you check the Bulk pins connections in layout? 

     There are *no* ones. When I imported the GDS file produced by Encounter in a way described above, the fresh library to which everything was imported had the standard cells, like INVERTER which I messed with before. And that Inverter, and all other type of pins have VDD! and GND! routed metals on top and bottom, but they do *not* have contacts to well or substrate. Which is weird right? I also did import the standard cell GDS manually from virtuoso to a separate library, and the layouts of each elemnts also do *not* have contacts to well and substrate.

     >You r transistors should be connected to these substrate connections using a diffusion layer pwell or nwell but it should not be needed to add substrate contact or nwell contact. 

    So that is how things done normally with most Kits right? I mean is that how the big digital projects get done then, tool (Encounter+Kit LEF) takes care not only for net interconnect but also properly should place Nwell/Substrate contacts, right? Turns out that it is not a case then for me.. Does it mean a *HUGE* nightmare to design/route/LVS in Virtuoso a really big digital project? Or maybe there is something I missed during setup of flow and thats why it appears like that? Because, actually theres not much to do, all one does is a) provide LEF, b) provide RTL synthesized verilog c) route d) export GDS, e) import in Virtuoso f) DRC in virtuoso g) LVS in virtuoso. Seems like I am stuck on (g) but if tool didnt place contacts (or didnt take care of it) then I am stuck with (f) too because I *must* place them.  

    So, the way it looks to me now is that lots of stuff is now concentrated on this issue of bulk pin connection. Because if I place it, the schematic would require it to be there. But standard CDL files usually dont have those entities. So it complains. So if I am correct, I must somehow 1) Make encounter to put bulk connections/contacts during routing 2) somehow resolve the substrate contact issue.

    You ever came across such situation? i.e. standard cell layouts without bulk connection and same during autorouting in Encounter? 

Reply

  • >Kabal, Is the layout view provided by your founder? 

    Yes. They provide GDS file, which I independently imported to my library, and could see all the layouts and open them in layout editor. And during GDS export from Encounter, I merged the final GDS of my design with the GDS file of the standard cells. That is how I had to do it for all the layers to show up correctly.

    >Did you check your layer map file and your rule deck? 

    During that export process I pointed to the MAP file provided by customer as well, that MAP file was specifically made for Soc2GDs transition. Rule deck? whats that? You mean LEF? yes they were provided to Encounter

     >Can you check the Bulk pins connections in layout? 

     There are *no* ones. When I imported the GDS file produced by Encounter in a way described above, the fresh library to which everything was imported had the standard cells, like INVERTER which I messed with before. And that Inverter, and all other type of pins have VDD! and GND! routed metals on top and bottom, but they do *not* have contacts to well or substrate. Which is weird right? I also did import the standard cell GDS manually from virtuoso to a separate library, and the layouts of each elemnts also do *not* have contacts to well and substrate.

     >You r transistors should be connected to these substrate connections using a diffusion layer pwell or nwell but it should not be needed to add substrate contact or nwell contact. 

    So that is how things done normally with most Kits right? I mean is that how the big digital projects get done then, tool (Encounter+Kit LEF) takes care not only for net interconnect but also properly should place Nwell/Substrate contacts, right? Turns out that it is not a case then for me.. Does it mean a *HUGE* nightmare to design/route/LVS in Virtuoso a really big digital project? Or maybe there is something I missed during setup of flow and thats why it appears like that? Because, actually theres not much to do, all one does is a) provide LEF, b) provide RTL synthesized verilog c) route d) export GDS, e) import in Virtuoso f) DRC in virtuoso g) LVS in virtuoso. Seems like I am stuck on (g) but if tool didnt place contacts (or didnt take care of it) then I am stuck with (f) too because I *must* place them.  

    So, the way it looks to me now is that lots of stuff is now concentrated on this issue of bulk pin connection. Because if I place it, the schematic would require it to be there. But standard CDL files usually dont have those entities. So it complains. So if I am correct, I must somehow 1) Make encounter to put bulk connections/contacts during routing 2) somehow resolve the substrate contact issue.

    You ever came across such situation? i.e. standard cell layouts without bulk connection and same during autorouting in Encounter? 

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.