I have successfully imported the layout from Encounter, and solved out the residual DRC errors, however; I am not sure now how to do LVS.
Before I had some problems with import which were covered in another subforums here and topics but I solved them all, right now I want to concentrate just on a specific LVS on Encounter Imported Layout issue.
Here are my actions:
1) get the verilog design synthesized properly and routed without geometry/connectivity violations in Encounter [DONE]
2) Properly export it to GDS file [DONE]
3) do saveNetlist -phys -includePowerGround from the Encounter, it basically produces a Physical Verilog netlist, which includes cell description + Power pins. [DONE]
4) Go to Cadence Virtuoso, do CIW->Import->Verilog, there I point to the physical verilog netlist produced by Encounter and also point to the newly created library based on technology kit with imported proper metal layers.
5) then i start the process of importing scehmatics for CDL, I see that the cells are created one after another, and the main big schematics is created, where each module of the schematic is the standard library cell. However, when I click and get inside that cell I see only ports, and no transistors.
It might look OK, since afterall it has imported physical VERILOG netlist, not a transistor schematic.
But problem starts when I try to produce CDL netlist using the IBM provided Perl script for the LVS. The final output of that script is MY_INSTANCE_NAME.netlist.lvs
However, when I start now doing LVS on the corrected/DRCed Layout, I get errors like:
a) nMOS on layout is unbound to any schematic device
b) pMOS on Layout is unbound to any schematic device
c) subC on Layout unbound to schematic device
Error (c) is OK, I can fix it simbly by adding the substrate contact in the imported schematics.
(reason for that is that DRC does not pass without proper amount of substrate contacts on a layout, so in an imported layout I added them.. but then again, I added it also in the schematic, so error (c) was gone)
However, what really weird is: why do errors (a) and (b) exist?
From one side, I understand, it does not SEE the transistors because the cells imported from physical verilog dont have one (because verilog describes hardware flow not transistor interconnect)
But from another side, why would it even try to find transistors?
Why does not it treat my imported layout cells as a standalone modules with just ports, because that is what they are.
I even tried creating CDL netlist in "Digital" format from the imported schematics view, same thing.
Am I missing something trivial here?
If you have in your top layout view some layout representation for the standard cells which contains transistors but your schematic view representing the standard cells are empty then your LVS tools is going to report them.
Most of the time founders provide a CDL file which contains the transistor description of your standard cells then you need to include into the netlist one your feed to your LVS file.
Ok, I do can find the CDL file with standard cells. It seems that I am kind of close to solution but still have some questions.
Now I guess question is, how exactly I include it? Here are my steps:
1) Create CDL netlist from schematic which is imported from verilog (that schematic contains only instances of standard cells)
2) Use the script to transfer CDL netlist to LVS format
3) Go to LVS, in the LVS include the schematic netlist in LVS format obtained from step (2), and also include pure CDL file from standard cell library with all descriptions of standard cells.
As a result, this time LVS doesnt fail, however; it reports about thousands of mismatched layout<->schematic devices, like transistor width mismatch etc.
Seems like I am really close, but just missing something, what else had to be done there?
We are making progress this is great.
In step 2 why did not you run teh same script ofr teh std cells cdl ? Isn't it required is the format already ok?
In order to easily debug it I would suggest that you look at one std cells at a time.
You could for exmaple run a LVS on one std cells like the most basic invertor that you have in your design.
Alright, in step 2 I did choose just CDL now. (i noticed that it doesnt matter)
Here are my actions/observations:
1) I opened schematics of imported inverter (again, its schematics contained only *pins* and nothing else)
2) Export netlist
3) Apply CDL processor to convert it to LVS netlist format
4) Go to layout, start LVS window, there point it to two files, one file produced from empty schematic in step (3), another file is std. lib CDL file.
As a result two major errors were reported like something described below:
a) Terminal B of pMos should be connected to VDD! instead of floating pin.
b) Terminal B of nMOS should be connected to GND! instead of floating pin.
At this stage, let me tell something: When I design for example some custom inverter by hand in my own libs, and when I lay it out, I always put Nwell and Substrate contacts in a layout. But in a schematic I put only substrate contact primitive. Then I pass LVS.
Now back to this issue, error (2) was manually corrected simply by putting Nwell contact, after that when I ran LVS it only reported me error (b)
However, when I try to correct error (b) by putting substrate contact and then run LVS, the LVS process *FAILS*, and in the log it says that substrate contact on a layout is unbound to schematic. I tried to put substrate contact with GND! connection on top in a schematic, it didnt help.
And by the way, is it kind of a pain generally one has to deal with when working with Encounter layout import? (what I mean is the mess around with nwell/substrate contacts) ?