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LVS on a layout imported from Encounter versus the Physical Verilog netlist

Kabal

 

 

I have successfully imported the layout from Encounter, and solved out the residual DRC errors, however; I am not sure now how to do LVS.

Before I had some problems with import which were covered in another subforums here and topics but I solved them all, right now I want to concentrate just on a specific LVS on Encounter Imported Layout issue. 

 

Here are my actions:

 

1) get the verilog design synthesized properly and routed without geometry/connectivity violations in Encounter [DONE] 

 

2) Properly export it to GDS file [DONE] 

 

3) do saveNetlist -phys -includePowerGround from the Encounter, it basically produces a Physical Verilog netlist, which includes cell description + Power pins. [DONE]

 

4) Go to Cadence Virtuoso, do CIW->Import->Verilog, there I point to the physical verilog netlist produced by  Encounter and also point to the newly created library based on technology kit with imported proper metal layers.

 

5) then i start the process of importing scehmatics for CDL, I see that the cells are created one after another, and the main big schematics is created, where each module of the schematic is the standard library cell. However, when I click and get inside that cell I see only ports, and no transistors.

 

It might look OK, since afterall it has imported physical VERILOG netlist, not a transistor schematic.

But problem starts when I try to produce CDL netlist using the IBM provided Perl script for the LVS. The final output of that script is MY_INSTANCE_NAME.netlist.lvs

 

However, when I start now doing LVS on the corrected/DRCed Layout, I get errors like:

a) nMOS on layout is unbound to any schematic device

b) pMOS on Layout is unbound to any schematic device

c) subC on Layout unbound to schematic device

 

Error (c) is OK, I can fix it simbly by adding the substrate contact in the imported schematics. 

(reason for that  is that DRC does not pass without proper amount of substrate contacts on a layout, so in an imported layout I added them.. but then again, I added it also in the schematic, so error (c) was gone)

 

However, what really weird is: why do errors (a) and (b) exist?

 

From one side, I understand, it does not SEE the transistors because the cells imported from physical verilog dont have one (because verilog describes hardware flow not transistor interconnect)

 

But from another side, why would it even try to find transistors?

 

Why does not it treat my imported layout cells as a standalone modules with just ports, because that is what they are.

 

I even tried creating CDL netlist in "Digital" format from the imported schematics view, same thing.

 

Am I missing something trivial here? 

 

Any ideas?


Parents

  • OK, following Solution 3, but I have problems with setting ignore on empty cells. I have three types of FILL cells: FILL1, FILL2, NWSX. And it seems to me that the ignoreCell avParameter of LVS only works for Layout view, not a Stream.

    But here is anothe thing I did, I think I am really close to solution:

    1) In the encounter after final routing done, add: FILL1, FILL2, NWSX

    2) Produce GDSII by merging with GDS of standard cells

    3) Import that GDSII in Layout in Virtuoso, guess what, now when I do DRC I *DO NOT* see those missing well/tap contact errors anymore. In other words, it looks like now DRC is clean (just some IO port misalignment on Pin layers, but that was fixed really quick). So, it looks that I do not have to add those substrate contacts in schematics or whatever to pass LVS, all I need now is just to pass LVS.

    However, problem is, that once I start doing LVS of this nicely imported layout with clean DRC, I again get errors like: FILL1, FILL2, NWSX not defined.. and that ignore method described above doesnt work.  Even though now, I do LVS over the Layout... so it should work. I attached picture showing avParameter for ignore cells. 

    I tried already all kinds of combinations, doing ignoreCell both for layout and schematic (by showing verilog file) in avCompare rules as well. its still same! LVS fails with saying that: FILL1, FILL2, NWSX is not defined.. it just doesnt make sense, am I missing something?

    Any ideas? 

Reply

  • OK, following Solution 3, but I have problems with setting ignore on empty cells. I have three types of FILL cells: FILL1, FILL2, NWSX. And it seems to me that the ignoreCell avParameter of LVS only works for Layout view, not a Stream.

    But here is anothe thing I did, I think I am really close to solution:

    1) In the encounter after final routing done, add: FILL1, FILL2, NWSX

    2) Produce GDSII by merging with GDS of standard cells

    3) Import that GDSII in Layout in Virtuoso, guess what, now when I do DRC I *DO NOT* see those missing well/tap contact errors anymore. In other words, it looks like now DRC is clean (just some IO port misalignment on Pin layers, but that was fixed really quick). So, it looks that I do not have to add those substrate contacts in schematics or whatever to pass LVS, all I need now is just to pass LVS.

    However, problem is, that once I start doing LVS of this nicely imported layout with clean DRC, I again get errors like: FILL1, FILL2, NWSX not defined.. and that ignore method described above doesnt work.  Even though now, I do LVS over the Layout... so it should work. I attached picture showing avParameter for ignore cells. 

    I tried already all kinds of combinations, doing ignoreCell both for layout and schematic (by showing verilog file) in avCompare rules as well. its still same! LVS fails with saying that: FILL1, FILL2, NWSX is not defined.. it just doesnt make sense, am I missing something?

    Any ideas? 

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