Reading a data file in Veriloga code

I tried your module and did not have the problem with reading the file, so I can only assume the issue you have is because either the path you've given is incorrect or that the permissions are such that you can't read the file.

I did however have a problem due to the fact that your arrays are [1:9] whereas the code tries to write (and read) from index 0, and so they should be defined as [0:9] (maybe [0:8] would be OK). But after fixing that, it ran (not sure whether it was correct, because I'm not sure what it's supposed to be doing).

So do as the error suggested, and check the path exists and that you have sufficient permissions to read it.

Regards,

Andrew.

 Thank you so much I corrected the code but it gives me this error, I'm wondering about the "idt" could be used for an expression like this or just with voltage/current signal?

RROR (VACOMP-2154):
        "/home/VxijwithFile/veriloga/veriloga.va",
        line 34: Encountered the `idt' analog operator embedded in a
        conditionally-executed statement or in an expression. The software does
        not support this use. Do not use the `idt' analog operator in a
        conditionally-executed statement or in an expression.

 -----------The code-------------
`include "constants.vams"
`include "disciplines.vams"

module VxijwithFile(x,n);
inout x,n;
electrical x,n;
real parameter c=1e-9,r=1e3,I=0,Vx0=1,t=5e-6;
integer mcd,retval,count,f;
real Vykl[1:9],a,vx,A[1:9],Vxij[1:9];
genvar i;
analog begin

 @(initial_step) begin

 mcd=$fopen("/home/Documents/scanftest.dat","r");
      retval=2;
      count=1;
      while(retval==2) begin
         retval=$fscanf(mcd,"%f, %f",a,vx);
         A[count]=a;
         Vxij[count]=vx;
         Vykl[count]=0.5*(abs(Vxij[count]+1)-abs(Vxij[count]-1));
         count=count+1;
      end
$fclose(mcd);

       f=0;
       for (i=1;i<10;i=i+1) begin
       f=f+A[f]*Vykl[f];

end
V(x,n) <+ exp(-t/(r*c))+idt(exp((t-c*r)/(r*c))*(f/c));

end
end


endmodule

Thank you,

Your contribution statement appears to be inside the begin/end block for @(initial_step), whereas it should be outside (it was earlier). So you have two end statements below the contribution statement (the V(x,n) <+ ... line), and one above - there should be two end statements above and one below.

Regards,

Andrew.

Thank you so much for your help. This error dissappeared I have another dc convergance error i'm trying to change the design.

Thanks again