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Reading a data file in Veriloga code

Sali

Dear all,

I'm a new user with Veriloga in Cadence I wrote the following model and created a symbol to simulated it with other components but I got the following error:

FATAL (VLOGA-5096):  16: I50:  Cannot open file 'scanftest' for reading. Check this file to verify that it exists and that you have permission to open it for reading and try again. The idea is reading the numbers from the file then store each colomn in a separete array to use it after in the claculations. where I must svae the data file, it is two colomns of 9 decimal numbers and thsi is the code:

`include "constants.vams"
`include "disciplines.vams"

module VxijwithFile(x);
inout x;
electrical x;
real parameter c=1e-9,r=1e3,I=0,Vx0=1,t=5e-6;
integer A[1:9], Vxij[1:9],mcd,retval,count,f;
real Vykl[1:9],a,vx;
genvar i;

analog begin
 @(initial_step) begin
      mcd=$fopen("/home/VxijwithFile/veriloga/scanftest","r");
      retval=2;
      count=0;
      while(retval==2) begin
         retval=$fscanf(mcd,"%f %f",a,vx);
         A[count]=a;
         Vxij[count]=vx;
         Vykl[count]=0.5*(abs(Vxij[count]+1)-abs(Vxij[count]-1));
count=count+1;
      end
$fclose(mcd);

       f=0;
       for (i=1;i<8;i=i+1) begin
       f=f+A[f]*Vykl[f];
       end
end
V(x) <+ exp(-t/(r*c))+idt(exp((t-c*r)/(r*c))*(f/c));

end

endmodule

 

thank you 

Parents

  •  Thank you so much I corrected the code but it gives me this error, I'm wondering about the "idt" could be used for an expression like this or just with voltage/current signal?

    RROR (VACOMP-2154):
            "/home/VxijwithFile/veriloga/veriloga.va",
            line 34: Encountered the `idt' analog operator embedded in a
            conditionally-executed statement or in an expression. The software does
            not support this use. Do not use the `idt' analog operator in a
            conditionally-executed statement or in an expression.

     -----------The code-------------
    `include "constants.vams"
    `include "disciplines.vams"

    module VxijwithFile(x,n);
    inout x,n;
    electrical x,n;
    real parameter c=1e-9,r=1e3,I=0,Vx0=1,t=5e-6;
    integer mcd,retval,count,f;
    real Vykl[1:9],a,vx,A[1:9],Vxij[1:9];
    genvar i;
    analog begin

     @(initial_step) begin

     mcd=$fopen("/home/Documents/scanftest.dat","r");
          retval=2;
          count=1;
          while(retval==2) begin
             retval=$fscanf(mcd,"%f, %f",a,vx);
             A[count]=a;
             Vxij[count]=vx;
             Vykl[count]=0.5*(abs(Vxij[count]+1)-abs(Vxij[count]-1));
             count=count+1;
          end
    $fclose(mcd);

           f=0;
           for (i=1;i<10;i=i+1) begin
           f=f+A[f]*Vykl[f];

    end
    V(x,n) <+ exp(-t/(r*c))+idt(exp((t-c*r)/(r*c))*(f/c));

    end
    end


    endmodule





     

    Thank you,

Reply

  •  Thank you so much I corrected the code but it gives me this error, I'm wondering about the "idt" could be used for an expression like this or just with voltage/current signal?

    RROR (VACOMP-2154):
            "/home/VxijwithFile/veriloga/veriloga.va",
            line 34: Encountered the `idt' analog operator embedded in a
            conditionally-executed statement or in an expression. The software does
            not support this use. Do not use the `idt' analog operator in a
            conditionally-executed statement or in an expression.

     -----------The code-------------
    `include "constants.vams"
    `include "disciplines.vams"

    module VxijwithFile(x,n);
    inout x,n;
    electrical x,n;
    real parameter c=1e-9,r=1e3,I=0,Vx0=1,t=5e-6;
    integer mcd,retval,count,f;
    real Vykl[1:9],a,vx,A[1:9],Vxij[1:9];
    genvar i;
    analog begin

     @(initial_step) begin

     mcd=$fopen("/home/Documents/scanftest.dat","r");
          retval=2;
          count=1;
          while(retval==2) begin
             retval=$fscanf(mcd,"%f, %f",a,vx);
             A[count]=a;
             Vxij[count]=vx;
             Vykl[count]=0.5*(abs(Vxij[count]+1)-abs(Vxij[count]-1));
             count=count+1;
          end
    $fclose(mcd);

           f=0;
           for (i=1;i<10;i=i+1) begin
           f=f+A[f]*Vykl[f];

    end
    V(x,n) <+ exp(-t/(r*c))+idt(exp((t-c*r)/(r*c))*(f/c));

    end
    end


    endmodule





     

    Thank you,

Children
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