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LVS versus physical Verilog from Encounter, Power Node Mismatch

Kabal

OK, my battle over the LVS versus the physical Verilog file exported from Encounter continues. Finally, I think I kind of managed at least to get LVS working without quitting with error. i.e. it does run and completes successfully.

However, right now I have another issue, which is basically netlist mismatch.  I am going to attach two files here, a picture with a snapshot of console window from which I export physical verilog from encounter, the LVS run options window where I show how I configure LVS before run. 

 Another file, is just LVS log output, where it tells what specifically does not match. Now let me discuss this, as you see it says something like: Layout net: GND! shorts to I__13/GND!

I kind of don't get it. I mean GND! is global ground and VDD! is global power, they MUST "short" to GND! and VDD! of each cell of course. why would LVS complain?
 
On the other hand, I know that globals cant be "shorted" to globals. But that is the way it was routed in encounter.
As you know, in encounter for the power we usually put VDD! and for ground GND! and each GND! and VDD! of each cell connects to that global VDD!  and GND!.
 
What is the proper way then to do it? 
 
Or what is the proper way then to tell LVS that it is "OK" that those lines are shorting.
 
(do not suggest something like cds_thru because I am doing LVS of layout versus the physical verilog file)
 
Any ideas? 
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