VerilogA models in Cadence

Dear all,

I need your help to how to finish this simulation I spent a lot of time learning VerilogA and the way of creating new models in Cadence

My circuit that I need to simulated it in Cadence is  

At the begining I tried to model three separate sources and connect them together in the schematic but it fails to simulate, then I tried to write all model in one cell view and connect it to the rest of the circuit, here I coudn't continue and I don't know how to connect it.

The schematic is in the following figure:

The transient analysis:

The verilogA code is :

// VerilogA for Chua12, VxijwithFile, veriloga

`include "constants.vams"

`include "disciplines.vams"

module VxijwithFile(x,xij,gnd);

inout x,xij,gnd;

electrical x,xij,gnd;

real parameter c=1e-9,r=1e3,I=0,Vx0=1;

integer mcd,retval,count,f;

real Vykl[1:9],a,vx,A[1:9],Vxij[1:9],Avy[1:9],sum,v1,v2,t;

branch(xij,gnd) ij;

genvar i; 

analog begin

   mcd=$fopen("/home/Documents/scanftest.dat","r");

      retval=2;

      count=1;

      sum=0;

      while(retval==2) begin

         retval=$fscanf(mcd,"%f, %f",a,vx);

         A[count]=a;

         Vxij[count]=vx;

         Vykl[count]=0.5*(abs(Vxij[count]+1)-abs(Vxij[count]-1));

         Avy[count]=A[count]*Vykl[count];

         sum=sum+Avy[count];

         count=count+1;

      end

$fclose(mcd);

       f=0;          

      for (i=1;i<10;i=i+1) begin 

       f=f+A[f]*Vykl[f];

       end      

v1=exp((t-c*r)/(r*c))*(f/c);

v2=idt(v1,0,10e-5);

V(x,gnd) <+ exp(-t/(r*c))+v2;

//I(xij,gnd) <+ sum;  

end

endmodule

The error I got:

Error found by spectre during IC analysis, during transient analysis `tran'.

    ERROR (SPECTRE-16080): No DC solution found (no convergence).  

The values for those nodes that did not converge on the last Newton iteration are given below.  The manner in which the convergence criteria were not satisfied is also given.

            Failed test: | Value | > RelTol*Ref + AbsTol

 Top 7 Residue too large Convergence failure:

    V(net4) = 0 V

        residue too large: | -1 A | > 5 mA + 1 pA

The following set of suggestions might help you avoid convergence difficulties.  Once you have a solution, write it to a nodeset file using the `write' parameter and read it back in on subsequent simulations using the `readns' parameter.

 1. Evaluate and resolve any notice, warning, or error messages.

 2. Perform sanity check on the parameter values using the parameter range checker (use ``+param param-limits-file'' as a command line argument) and heed any warnings.  Print the minimum and maximum parameter value using the `info' analysis.  Ensure that the bounds given for instance, model, output, temperature-dependent, and operating-point (if possible) parameters are reasonable.

 3. Check the direction of both independent and dependent current sources. Convergence problems might result if current sources are connected such that they force current backward through diodes.

 4.  Enable diagnostic messages by setting option `diagnose=yes'.

 5. Small floating resistors connected to high impedance nodes might cause convergence difficulties. Avoid very small floating resistors, particularly small parasitic resistors in semiconductors. Instead, use voltage sources or iprobes to measure current.

 6. If you have an estimate of what the solution should be, use nodeset statements or a nodeset file and set as many nodes as possible.

 7. Use realistic device models. Check all component parameters, particularly nonlinear device model parameters, to ensure that they are reasonable.

 8. If simulating a bipolar analog circuit, ensure the region parameter on all transistors and diodes is set correctly.

 9. Loosen tolerances, particularly absolute tolerances like `iabstol' (on options statement). If tolerances are set too tight, they might preclude convergence.

10. If analysis fails at an extreme temperature, but succeeds at room temperature, try adding a DC analysis that sweeps temperature.  Start at room temperature, sweep to the extreme temperature, and write the final solution to a nodeset file.

11. Increase the value of gmin (on options statement).

12. Use numeric pivoting in the sparse matrix factorization by setting `pivotdc=yes' (on options statement). Sometimes, it is also necessary to increase the pivot threshold to somewhere in the range of 0.1 to 0.5 using `pivrel' (on options statement).

13. Try to simplify the nonlinear component models in order to avoid regions in the model that might contribute to convergence problems.

14. Divide the circuit into smaller pieces and simulate them individually, but ensure that the results will be close to what they would be if you had simulated the whole circuit.  Use the results to generate nodesets for the whole circuit.

15. If all else fails, replace the DC analysis with a transient analysis and modify all the independent sources to start at zero and ramp to their DC values. Run the transient analysis well beyond the time when all the sources have reached their final value (remember that transient analysis is very cheap when all of the signals in the circuit are not changing) and write the final point to a nodeset file. To make the transient analysis more efficient, set the integration method to backward Euler (`method=euler') and loosen the local truncation error criteria by increasing `lteratio', say to 50. Occasionally, this approach will fail or be very slow because the circuit contains an oscillator.  Often times the oscillation can be eliminated for the sake of finding the dc solution by setting the minimum capacitance from each node to ground (`cmin') to a large value.

Analysis `tran' was terminated prematurely due to an error.

finalTimeOP: writing operating point information to rawfile. 

Could you please help me.

Thanks