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  3. ARM standard cell libraries for 65nm process, there are...

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ARM standard cell libraries for 65nm process, there are no schematic reps

pfrogge
pfrogge over 11 years ago

Been out of the IC design industry for a few years, so this is new to me, how can one LVS a design when there are no schematic views for cells?  How can one spectre sim a schematic that has a mix of standard cells and transistors or other blocks when no schematic view exist for standard cells.
thanks
Perry 
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  • Andrew Beckett
    Andrew Beckett over 11 years ago

     Precisely how you would LVS it depends upon the LVS tool you're using. Assura and PVS and Dracula (and probably Mentor's Calibre, I'm sure), allow you to read in multiple CDL netlists; you could generate a CDL netlist from Virtuoso and then read in this together with the CDL netlist that ARM have provided you with.

    For simulation, you may have been provided with a SPICE representation too (which may have more detail than the CDL). You can include this in ADE as a model file. It is important to ensure that the termOrder in the CDF for spectre (and for auCdl) for each of the standard cells matches the order in the netlist you're including - since spectre (and CDL) are pass-by-order. I'm assuming you already have symbols for the the cells.

    You may also want to look at Tawna's blog entry on setting this kind of thing up.

    Regards,

    Andrew.

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  • sadegh
    sadegh over 11 years ago

    hi andrew

    how can I link up the 65nm library to my cadence after downloading all the files from mosis?

    now I am working by gdpk045 in my cadence virtuoso, but i provided the 65 nm files. the problem is I dont know how to link them with my cadence software? 

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  • Andrew Beckett
    Andrew Beckett over 11 years ago

    I have no idea, as I'm not familiar with the MOSIS files. Could you ask them?

    Maybe somebody else in the community who is familiar with the MOSIS kits can answer this.

    Andrew.

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