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simulating verilog and schematics in spectre

engrMunna

 Hi

Version use: Virtuoso IC6.1.5-64b.500.6 MMSIM 7.2

 I am simulating a verilogA deisgn along with some schematics  in spectre through analog deisgn enviroment. When i run the simulation I get the folloiwing error:

Error found by spectre during AHDL read-in.
    ERROR (VACOMP-2125): "path/cellname/veriloga/veriloga.va", near line 53: segment error for symbol: rfin
    ERROR (VACOMP-1816): Exiting AHDL compilation.

Time for Elaboration: CPU = 111.982 ms, elapsed = 121.443 ms.
Time accumulated: CPU = 3.08353 s, elapsed = 3.29656 s.
Peak resident memory used = 156 Mbytes.

spectre terminated prematurely due to fatal error.

Parents

  •   Solved. It was an error in the code. not a syntax error probably thats why it compiled.

    And for the benefit of others: the problem was that "rfin" is a voltage input to the verilogA block. I used "rfin" in a trasnsition statement as: V(out) <+ transition(rfin, delay). this was wrong and thats why it gave the error. The correct way to do it is V(out) <+ transition(V(rfin),delay)

     

    where as rfin is deifned as an electrical type.

Reply

  •   Solved. It was an error in the code. not a syntax error probably thats why it compiled.

    And for the benefit of others: the problem was that "rfin" is a voltage input to the verilogA block. I used "rfin" in a trasnsition statement as: V(out) <+ transition(rfin, delay). this was wrong and thats why it gave the error. The correct way to do it is V(out) <+ transition(V(rfin),delay)

     

    where as rfin is deifned as an electrical type.

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