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simulating verilog and schematics in spectre

engrMunna

 Hi

Version use: Virtuoso IC6.1.5-64b.500.6 MMSIM 7.2

 I am simulating a verilogA deisgn along with some schematics  in spectre through analog deisgn enviroment. When i run the simulation I get the folloiwing error:

Error found by spectre during AHDL read-in.
    ERROR (VACOMP-2125): "path/cellname/veriloga/veriloga.va", near line 53: segment error for symbol: rfin
    ERROR (VACOMP-1816): Exiting AHDL compilation.

Time for Elaboration: CPU = 111.982 ms, elapsed = 121.443 ms.
Time accumulated: CPU = 3.08353 s, elapsed = 3.29656 s.
Peak resident memory used = 156 Mbytes.

spectre terminated prematurely due to fatal error.

Parents

  • Do you have spectre in your UNIX path and can it run? Try typing "spectre -W" from the UNIX command line that you're running virtuoso from and show what it reports.

    The "Read veriloga" bit is correct - this is how it should work.

    The netlisting error is unsurprising - if the checker doesn't run, it also can't extract the pins used in the VerilogA, and hence it doesn't 

    Regards,

    Andrew.

Reply

  • Do you have spectre in your UNIX path and can it run? Try typing "spectre -W" from the UNIX command line that you're running virtuoso from and show what it reports.

    The "Read veriloga" bit is correct - this is how it should work.

    The netlisting error is unsurprising - if the checker doesn't run, it also can't extract the pins used in the VerilogA, and hence it doesn't 

    Regards,

    Andrew.

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