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LVS unable to check the NMOS source connectivity to the ground

sutej

Hi all,

I am using Cadence IC 6.15  and using Assura for DRC, LVS and extraction.My LVS check shows no errors and says all the cells are matched. However, after running the post layout simulation I found that the results are abnormal. After spending more time on rechecking the layout...I found that at one place I did not connect the NMOS source to the ground although it is connected to the substrate and in schematic both the substrate and source were connected together to the ground. After fixing this error post layout simulation results are okay. I presume that the LVS tool is considering the NMOS ground connection through the substrate which is connected to the ground at some other place in the circuit. Could any one please let me know how to fix such an exceptions. I have a very big design and it is becoming increasingly difficult to manually keep tab of this exception. Any Immediate reply is very much appreciable as my tape out date is nearing by.

 

Regards,

Sutej 

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