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A stochastic model in Verilog A for Monte Carlo simulation

UUinfini

 Hello Guys,

I have a problem for Veriglog A in Cadence, I hope you can help me. In fact I need to elaborate a stochastic model by coding in Verilog A executed under Cadence. My aim is to offer a model with which the customers can do the Monte Carlo Analysis. But I used the functions like "$random", "$temperature" etc. to generate a seed for obtaining a parameter which changes each time of simulation. But finally it changes just according to the real time of simulation, but not according to different times of simulation. Do you have any experiences like this? Thank you for you response.

Best regards,

UU

Parents

  • The first problem is that your "source.scs" should not have the ahdl_include statement in it. Since you've created a cellView in Virtuoso for that cell containing the veriloga code, the spectre netlister will automatically add the "ahdl_include" for you. So you've defined it twice because of this.

    The second issue is that (for some reason) the instance of source in your schematic seems to be passing seedin - which it shouldn't be. Did you set the value on the instance? I suspect that maybe there was an issue with the veriloga parser in MMSIM10.1 which meant that it mistakenly identified this cds_inherited_param as a normal parameter - I don't have that version to hand though so I can't test that.

    Could you use Tools->CDF->Edit in the CIW, set it to "Base", and pick the lib and "source" cell that you've created, and then use the "CDF Dump" button to dump out the CDF for the "source" cell, and then post it here (maybe as an attachment via the Options tab)? Then I can see what's going on in your case.

    Kind Regards,

    Andrew.

Reply

  • The first problem is that your "source.scs" should not have the ahdl_include statement in it. Since you've created a cellView in Virtuoso for that cell containing the veriloga code, the spectre netlister will automatically add the "ahdl_include" for you. So you've defined it twice because of this.

    The second issue is that (for some reason) the instance of source in your schematic seems to be passing seedin - which it shouldn't be. Did you set the value on the instance? I suspect that maybe there was an issue with the veriloga parser in MMSIM10.1 which meant that it mistakenly identified this cds_inherited_param as a normal parameter - I don't have that version to hand though so I can't test that.

    Could you use Tools->CDF->Edit in the CIW, set it to "Base", and pick the lib and "source" cell that you've created, and then use the "CDF Dump" button to dump out the CDF for the "source" cell, and then post it here (maybe as an attachment via the Options tab)? Then I can see what's going on in your case.

    Kind Regards,

    Andrew.

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