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LVS Operation suddenly broke

Kabal

I have several previously submitted (and even tested) and successfully DRC'ed/LVS'ed designs of some amplifiers etc. Now I want to perform LVS again since I want to start another design based on old one, and suddenly LVS exists with these errors:


*ERROR* cell 'ind' is not defined.
*ERROR* cell 'pcdcap' is not defined.
*ERROR* cell 'bondpad' is not defined.

I have no idea what could go wrong? Same layout was LVS'ed nicely before with inductors and with above mentioned devices.

Any ideas what exactly could break suddenly?


 

Parents

  • Andrew, I checked, those cells are inside the CDL netlist. I am attaching the final exported from schematics netlist for LVS.

    By the way, I noticed that there is already update available for my kit from foundry, I updated to the latest version of the kit, then I pulled up my basic inverter, exported its netlist, and DRC'ed and LVS'ed its layout, all worked! No errors!

    But now, I again go to some template frame, which has bondpads and some esd cells/clamps. And again I get errors saying bondpad not defined! It does not make any sense!

    Here is the output of LVS when it quits with error:

     Reading schematic network

     inputting netlist /media/cadence/runs/schematic/TOP_frame_template2/TOP_frame_template2.netlist.lvs

    *WARNING* *.EQUATION is not supported

    *WARNING* *.MEGA is not supported

    *WARNING* *.PIN is not supported

    *WARNING* The capability to discard or ignore devices is not available

              Therefore all devices were included in the output

              Even though no *.BIPOLAR command was found

    Reading layout network

     inputting network ./runs/LVS/TOP_frame_template2/TOP_frame_template2.ldb

    *ERROR* cell 'pcdcap' is not defined.

    *ERROR* cell 'bondpad' is not defined.


    Finished /home/soft/cadence/assura41/tools/assura/bin/nvn


    *WARNING* /home/soft/cadence/assura41/tools/assura/bin/nvn exit with bad status

    *WARNING* Status 256

    *WARNING* Assura execution terminated


    *WARNING* An error occurred during Nvn PreExtraction.

    LVS preprocessing requires a successful run of Nvn.

    Assura will now terminate.


    Any ideas where else should I look into? I am amazed that I even updated the whole kit, and successfully DRC/LVS'ed the inverter with transistors, but the design of some template pad frame with PADs and ESD cells gives me this error. 

    What else could go wrong?
    TOP_frame_template2.netlist.zip
Reply

  • Andrew, I checked, those cells are inside the CDL netlist. I am attaching the final exported from schematics netlist for LVS.

    By the way, I noticed that there is already update available for my kit from foundry, I updated to the latest version of the kit, then I pulled up my basic inverter, exported its netlist, and DRC'ed and LVS'ed its layout, all worked! No errors!

    But now, I again go to some template frame, which has bondpads and some esd cells/clamps. And again I get errors saying bondpad not defined! It does not make any sense!

    Here is the output of LVS when it quits with error:

     Reading schematic network

     inputting netlist /media/cadence/runs/schematic/TOP_frame_template2/TOP_frame_template2.netlist.lvs

    *WARNING* *.EQUATION is not supported

    *WARNING* *.MEGA is not supported

    *WARNING* *.PIN is not supported

    *WARNING* The capability to discard or ignore devices is not available

              Therefore all devices were included in the output

              Even though no *.BIPOLAR command was found

    Reading layout network

     inputting network ./runs/LVS/TOP_frame_template2/TOP_frame_template2.ldb

    *ERROR* cell 'pcdcap' is not defined.

    *ERROR* cell 'bondpad' is not defined.


    Finished /home/soft/cadence/assura41/tools/assura/bin/nvn


    *WARNING* /home/soft/cadence/assura41/tools/assura/bin/nvn exit with bad status

    *WARNING* Status 256

    *WARNING* Assura execution terminated


    *WARNING* An error occurred during Nvn PreExtraction.

    LVS preprocessing requires a successful run of Nvn.

    Assura will now terminate.


    Any ideas where else should I look into? I am amazed that I even updated the whole kit, and successfully DRC/LVS'ed the inverter with transistors, but the design of some template pad frame with PADs and ESD cells gives me this error. 

    What else could go wrong?
    TOP_frame_template2.netlist.zip
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