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LVS Operation suddenly broke

Kabal

I have several previously submitted (and even tested) and successfully DRC'ed/LVS'ed designs of some amplifiers etc. Now I want to perform LVS again since I want to start another design based on old one, and suddenly LVS exists with these errors:


*ERROR* cell 'ind' is not defined.
*ERROR* cell 'pcdcap' is not defined.
*ERROR* cell 'bondpad' is not defined.

I have no idea what could go wrong? Same layout was LVS'ed nicely before with inductors and with above mentioned devices.

Any ideas what exactly could break suddenly?


 

  • Assuming that you're using Assura LVS (from previous posts), are you:

    1. Doing blackbox LVS?
    2. Using CDL as the netlist for the schematic side?

    Those are just the first questions that come to mind - it's hard to be sure without knowing a bit of context.

    Regards,

    Andrew.

  • Thanks for reply,

    1) Yes, I am using Assura LVS.
    2) I am not doing blackbox LVS, I just have custom schematics with transistors and other different elements, then I export the netlist, then I pass it through the LVS script as always and export to final netlist for LVS in CDL format.

    Always been doing it and it worked, but now it does not. The funny thing is, when I try to LVS one of the inverters I have with just two transistors, it is OK. But when I try to LVS something with inductors, bondpads, caps etc.. it gives errors like I shown.

    And again, all circuits worked before, and were even manufactured and tested. Not sure what on earth could go wrong there?

  • Can you check if those cells are missing from the CDL netlist? Are the instances there but no subckt definition?

    Regards,

    Andrew.

  • Andrew, I checked, those cells are inside the CDL netlist. I am attaching the final exported from schematics netlist for LVS.

    By the way, I noticed that there is already update available for my kit from foundry, I updated to the latest version of the kit, then I pulled up my basic inverter, exported its netlist, and DRC'ed and LVS'ed its layout, all worked! No errors!

    But now, I again go to some template frame, which has bondpads and some esd cells/clamps. And again I get errors saying bondpad not defined! It does not make any sense!

    Here is the output of LVS when it quits with error:

     Reading schematic network

     inputting netlist /media/cadence/runs/schematic/TOP_frame_template2/TOP_frame_template2.netlist.lvs

    *WARNING* *.EQUATION is not supported

    *WARNING* *.MEGA is not supported

    *WARNING* *.PIN is not supported

    *WARNING* The capability to discard or ignore devices is not available

              Therefore all devices were included in the output

              Even though no *.BIPOLAR command was found

    Reading layout network

     inputting network ./runs/LVS/TOP_frame_template2/TOP_frame_template2.ldb

    *ERROR* cell 'pcdcap' is not defined.

    *ERROR* cell 'bondpad' is not defined.


    Finished /home/soft/cadence/assura41/tools/assura/bin/nvn


    *WARNING* /home/soft/cadence/assura41/tools/assura/bin/nvn exit with bad status

    *WARNING* Status 256

    *WARNING* Assura execution terminated


    *WARNING* An error occurred during Nvn PreExtraction.

    LVS preprocessing requires a successful run of Nvn.

    Assura will now terminate.


    Any ideas where else should I look into? I am amazed that I even updated the whole kit, and successfully DRC/LVS'ed the inverter with transistors, but the design of some template pad frame with PADs and ESD cells gives me this error. 

    What else could go wrong?
    TOP_frame_template2.netlist.zip

  • Alright, it broke because the subcircuit.cdl file which had description of those cells was not included during netlist export operation (it just suddenly disappeared from the menu). The thing is, this line with path to that file was forever in that menu, and I just didn't notice its absence at the beginning. 

     Now it works. 

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