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LVS Operation suddenly broke

Kabal

I have several previously submitted (and even tested) and successfully DRC'ed/LVS'ed designs of some amplifiers etc. Now I want to perform LVS again since I want to start another design based on old one, and suddenly LVS exists with these errors:


*ERROR* cell 'ind' is not defined.
*ERROR* cell 'pcdcap' is not defined.
*ERROR* cell 'bondpad' is not defined.

I have no idea what could go wrong? Same layout was LVS'ed nicely before with inductors and with above mentioned devices.

Any ideas what exactly could break suddenly?


 

Parents

  • Alright, it broke because the subcircuit.cdl file which had description of those cells was not included during netlist export operation (it just suddenly disappeared from the menu). The thing is, this line with path to that file was forever in that menu, and I just didn't notice its absence at the beginning. 

     Now it works. 

Reply

  • Alright, it broke because the subcircuit.cdl file which had description of those cells was not included during netlist export operation (it just suddenly disappeared from the menu). The thing is, this line with path to that file was forever in that menu, and I just didn't notice its absence at the beginning. 

     Now it works. 

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