CDL export error...

Copying the symbol to schematic doesn't sound a sensible thing to do. Copying to auCdl would be more sensible. You'll also need the auCdl simInfo section in the CDF (Tools->CDF->Edit in the CIW) for the component so that it knows how to netlist it.

What views do you have for the 3Vnfet?

Regards,

Andrew.

The views I have for 3Vnfet are: auLvs, hspiceS, ivpcell, lvs, spectre, spectreS, and symbol.

the auCdl simInfo in the CDF is already set and use the Netlist procedure ansCdlCompPrim.

Regards,

In that case it should just be a matter of adding the stopping view - copying the symbol to the auCdl view.

You don't want to add a schematic view, because that could break other netlisters/configs where you have schematic early in the switch view list.

Regards,

Andrew.

OK thanks, but I don't see any stopping view in the "edit simulation information " box in CDF. Do you mean stop view list in the ADE environment options?

regards

Stopping views are not defined in the CDF. The simulation information section of the CDF describes how to netlist a component for each netlister (e.g. spectre, spectreS, hspiceD, auLvs, auCdl).

Stopping views are defined for a particular netlister. They end up in a file called "si.env" which the netlisting system reads. In ADE, you can set this up on the Setup->Environment form, or if you use a config view, you can define it there.

For CDL netlisting, there's no UI to define the switch and stop list. Instead it's defined in the .simrc file. However, suffice to say, the default stop list for most netlisters contains a view with the same name as the netlister. So for auLvs, the stop list would include "auLvs", and for auCdl it would include a view called "auCdl".

In your case, the switch list for auCdl contains both schematic and auCdl. So when it encounters an instance of your transistor, it tries to switch into one of those views (auCdl or schematic, in that order), as it descends the hierarchy. Once it's switched into that view, it then checks to see if the view it switched into is in the stop list (auCdl will be in the stop list, schematic won't). So in your original method of solving this problem, it would then try to traverse the schematic view to see if there is any further hierarchy. Since the schematic was actually a symbol, it had no hierarchy. You may have found that you got an empty SUBCKT definition for the 3Vnfet though, which you probably don't want.

If you'd copied the symbol to auCdl instead, it would have descended into that, found that it's in the stop list, and then netlisted it according to the information in the auCdl simination info in the CDF (this simInfo is used for "primitive" components - i.e. leaf level cells - there's no further hierarchy to traverse, so it needs to know how to netlist the component - things like terminal order, instance parameters and so on).

Regards,

Andrew.

Yes you are right, when copying symbol to schematic, the netlist is made but the transistors don't appear in.

I finally copy symbol to auCdl and it works!!! the transistors are generated in the netlist.

thanks

Regards,

 Hi Benoit,

I think that you will need a .simrc file with the following entry in it:

 auCdlCDFPinCntrl=t

This should enable the CDF term order to control the pin order in the netlist, rather than using the default which is, I think, inputs, output and then inouts.  You are using the "analog" CDL netlister and not the "digital" CDL netlister, hence the "auCdl" prefix.

Hope it helps!

Lawrence.

I meet the similar problem when lvs with dracula,maybe you can help me!error：unable to descend into any of the views defined in the view list ：“aucdl schematic” for instance I120 in the cell mult4.But I do not find the I120 in the schematic .After I corrected some instances the error appeared.