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CDL export error...

archive
archive over 17 years ago

Hi everybody...


I try to make the Cdl export of a small Cell (1 resistance and 4 3Vnfet), But it failed. the error I get is: Netlister: unable to descend into any of the views defined in the view liste: "auCdl schematic" for instance M0 in Cell 3Vnfet.

n Cell 3Vnfet, when I copy "symbol" folder and rename it "schematic", I don't get this error anymore. But is it right to do that?? Or may I resolve this problem by another way!!

Thanks

ps: I use spectre simulator


Originally posted in cdnusers.org by isazul
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  • archive
    archive over 17 years ago

    Stopping views are not defined in the CDF. The simulation information section of the CDF describes how to netlist a component for each netlister (e.g. spectre, spectreS, hspiceD, auLvs, auCdl).

    Stopping views are defined for a particular netlister. They end up in a file called "si.env" which the netlisting system reads. In ADE, you can set this up on the Setup->Environment form, or if you use a config view, you can define it there.

    For CDL netlisting, there's no UI to define the switch and stop list. Instead it's defined in the .simrc file. However, suffice to say, the default stop list for most netlisters contains a view with the same name as the netlister. So for auLvs, the stop list would include "auLvs", and for auCdl it would include a view called "auCdl".

    In your case, the switch list for auCdl contains both schematic and auCdl. So when it encounters an instance of your transistor, it tries to switch into one of those views (auCdl or schematic, in that order), as it descends the hierarchy. Once it's switched into that view, it then checks to see if the view it switched into is in the stop list (auCdl will be in the stop list, schematic won't). So in your original method of solving this problem, it would then try to traverse the schematic view to see if there is any further hierarchy. Since the schematic was actually a symbol, it had no hierarchy. You may have found that you got an empty SUBCKT definition for the 3Vnfet though, which you probably don't want.

    If you'd copied the symbol to auCdl instead, it would have descended into that, found that it's in the stop list, and then netlisted it according to the information in the auCdl simination info in the CDF (this simInfo is used for "primitive" components - i.e. leaf level cells - there's no further hierarchy to traverse, so it needs to know how to netlist the component - things like terminal order, instance parameters and so on).

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
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  • archive
    archive over 17 years ago

    Stopping views are not defined in the CDF. The simulation information section of the CDF describes how to netlist a component for each netlister (e.g. spectre, spectreS, hspiceD, auLvs, auCdl).

    Stopping views are defined for a particular netlister. They end up in a file called "si.env" which the netlisting system reads. In ADE, you can set this up on the Setup->Environment form, or if you use a config view, you can define it there.

    For CDL netlisting, there's no UI to define the switch and stop list. Instead it's defined in the .simrc file. However, suffice to say, the default stop list for most netlisters contains a view with the same name as the netlister. So for auLvs, the stop list would include "auLvs", and for auCdl it would include a view called "auCdl".

    In your case, the switch list for auCdl contains both schematic and auCdl. So when it encounters an instance of your transistor, it tries to switch into one of those views (auCdl or schematic, in that order), as it descends the hierarchy. Once it's switched into that view, it then checks to see if the view it switched into is in the stop list (auCdl will be in the stop list, schematic won't). So in your original method of solving this problem, it would then try to traverse the schematic view to see if there is any further hierarchy. Since the schematic was actually a symbol, it had no hierarchy. You may have found that you got an empty SUBCKT definition for the 3Vnfet though, which you probably don't want.

    If you'd copied the symbol to auCdl instead, it would have descended into that, found that it's in the stop list, and then netlisted it according to the information in the auCdl simination info in the CDF (this simInfo is used for "primitive" components - i.e. leaf level cells - there's no further hierarchy to traverse, so it needs to know how to netlist the component - things like terminal order, instance parameters and so on).

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
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