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Abstract Generator : ERROR (ABS-216) [SOLVED], ERROR (ABS-218) [SOLVED], ERROR (ABS-263)

Hello,

I would like to generate the LEF view from a layout.oa (which contains layers up to M1) view for a simple cell (inverter) in 40LP Technology.

First step is to generate the abstract view, then the LEF view.

I am using the tool : Abstract Generator.

I have an issue, for the abstract view generation, when I load the library/tech file (cf. below).

INFO (ABS-127): Attaching the cmos045_tech_abstract technology library to the library_test_place_route_lef library.

LOG (ABS-212): Verifying Technology Data...

ERROR (ABS-216): There are insufficient metal layers defined in the current design. You must define at least two metal layers in the validLayers subsection of LEFDefaultRouteSpec constraint group of the technology file. These layers must have the layer function "metal" in the functions section. Update the technology file and attach it again.

INFO (ABS-253): Created the required DNW , pin layer-purpose pair in the technology file.

INFO (ABS-253): Created the required DNW , boundary layer-purpose pair in the technology file.

INFO (ABS-232): Layer summary: 0 metal layer(s), 9 via layer(s), 3 poly layer(s), and 8 diff layer(s) found

INFO (ABS-234): Via summary: 40 valid via(s) found

Tool used :

.../uniopus_oa/cadence_amsams2010.2c_mmsim/lnx/tools/dfII/bin/abstract

I have seen some messages in the forum regarding this topic, but no answer to them :

www.cadence.com/.../1312866.aspx

www.cadence.com/.../1313188.aspx

I had previoulsy : ERROR (ABS-218): There are no vias specified in the technology file. Which I solved adding the following lines in the tech file (see the 2 forum messages above) :

;********************************

; CONSTRAINT GROUPS

;********************************

constraintGroups(

;( group [override] )

;( ----- ---------- )

( "LEFDefaultRouteSpec" nil "LEFDefaultRouteSpec"

interconnect(

( validLayers ( ( AP drawing) ( AP tile) ( AP net) ( AP pin) ( CB drawing) ( CB pin) ( CB net) ( M7Z drawing) ( M7Z tile) ( M7Z pin) ( M7Z net) ( VIA6Z drawing) ( VIA6Z net) ( VIA6Z pin) ( M6Z drawing) ( M6Z tile) ( M6Z pin) ( M6Z net) ( VIA5Z drawing) ( VIA5Z pin) ( VIA5Z net) ( M5X drawing) ( M5X tile) ( M5X tile_O) ( M5X pin) ( M5X net) ( VIA4X drawing) ( VIA4X pin) ( VIA4X net) ( M4X drawing) ( M4X tile) ( M4X tile_O) ( M4X pin) ( M4X net) ( VIA3X drawing) ( VIA3X pin) ( VIA3X net) ( M3X drawing) ( M3X tile) ( M3X tile_O) ( M3X pin) ( M3X net) ( VIA2X drawing) ( VIA2X pin) ( VIA2X net) ( M2X drawing) ( M2X tile) ( M2X tile_O) ( M2X pin) ( M2X net) ( VIA1X drawing) ( VIA1X pin) ( VIA1X net) ( M1 drawing) ( M1 tile) ( M1 tile_O) ( M1 pin) ( M1 net) ( CO drawing) ( CO net) ( CO pin) ( PO drawing) ( PO tile) ( PO tile_O) ( PO filltr) ( PO net) ( PO pin) ( OD drawing) ( OD tile) ( OD tile_O) ( OD filltr) ( OD net) ( OD pin) PP NP ( NW drawing) ( NW net) ( NW pin) CutOxideWithPoly CutSubWithNwell d_pwell ) )

( validVias (M1_NW M1__NW M2X_M1_via M2X_M1_V_via M3X_M2X_via M3X_M2X_H_via M4X_M3X_via M4X_M3X_V_via M5X_M4X_via M5X_M4X_H_via M6Z_M5X_via M6Z_M5X_V_via M7Z_M6Z_via M7Z_M6Z_H_via AP_M7Z_via M1_POLYP M1_POLYN PTAP NTAP M1_POD M1_NOD M1__PO M1__PO_H M1_OD M1_PO M1_PO_H M2X_M1 M2X_M1_V M3X_M2X M3X_M2X_H M4X_M3X M4X_M3X_V M5X_M4X M5X_M4X_H M6Z_M5X M6Z_M5X_V M7Z_M6Z M7Z_M6Z_H AP_M7Z FI_AP ) )

) ;interconnect

) ;LEFDefaultRouteSpec

Some more extract of the tech file :

********************************

; LAYER RULES

;********************************

layerRules(

equivalentLayers(

;( list of layers )

;( -------------- )

( ("PO" "drawing") ("PO" "tile") ("PO" "tile_O") ("PO" "filltr") ("PO" "mask") )

( ("M1" "drawing") ("M1" "tile") ("M1" "tile_O") )

( ("M2X" "drawing") ("M2X" "tile") ("M2X" "tile_O") ("M2X" "connector") )

( ("M3X" "drawing") ("M3X" "tile") ("M3X" "tile_O") ("M3X" "connector") )

( ("M4X" "drawing") ("M4X" "tile") ("M4X" "tile_O") ("M4X" "connector") )

( ("M5X" "drawing") ("M5X" "tile") ("M5X" "tile_O") ("M5X" "connector") )

( ("M6Z" "drawing") ("M6Z" "tile") ("M6Z" "connector") )

( ("M7Z" "drawing") ("M7Z" "tile") ("M7Z" "connector") )

( ("AP" "drawing") ("AP" "tile") ("AP" "connector") )

) ;equivalentLayers

functions(

;( layer function [maskNumber])

;( ----- -------- ------------)

( DNW "nwell" 0 )

( NW "nwell" 1 )

( OD "diff" 2 )

( DCO "nplus" 3 )

( PO "poly" 4 )

( VTH_N "nplus" 5 )

( VTL_N "nplus" 6 )

( NP "nplus" 7 )

( VTH_P "pplus" 8 )

( VTL_P "pplus" 9 )

( PP "pplus" 10 )

( CO "cut" 11 )

( M1 "metal" 12 )

( VIA1X "cut" 13 )

( M2X "metal" 14 )

I cannot have access to : $CDSHOME/tools/dfII/samples/tutorials/abstract

I would be very grateful for any help.

Parents

samung over 11 years ago

OK, I found this one :
http://lost-contact.mit.edu/afs/rose-hulman.edu/cadence-0910/IC610/doc/abstract/appD.html I solved ABS-218 thanks to it :

;********************************
; CONSTRAINT GROUPS
;********************************
constraintGroups(

;( group [override] )
;( ----- ---------- )
( "LEFDefaultRouteSpec" nil "LEFDefaultRouteSpec"

interconnect(
( validLayers (AP CB M7Z VIA6Z M6Z VIA5Z M5X VIA4X M4X VIA3X M3X VIA2X M2X VIA1X M1 CO PO ) )
( validVias (M1_NW M1__NW M2X_M1_via M2X_M1_V_via M3X_M2X_via M3X_M2X_H_via M4X_M3X_via M4X_M3X_V_via M5X_M4X_via M5X_M4X_H_via M6Z_M5X_via M6Z_M5X_V_via M7Z_M6Z_via M7Z_M6Z_H_via AP_M7Z_via M1_POLYP M1_POLYN PTAP NTAP M1_POD M1_NOD M1__PO M1__PO_H M1_OD M1_PO M1_PO_H M2X_M1 M2X_M1_V M3X_M2X M3X_M2X_H M4X_M3X M4X_M3X_V M5X_M4X M5X_M4X_H M6Z_M5X M6Z_M5X_V M7Z_M6Z M7Z_M6Z_H AP_M7Z FI_AP ) )
) ;interconnect
) ;LEFDefaultRouteSpec
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samung over 11 years ago

OK, I found this one :
http://lost-contact.mit.edu/afs/rose-hulman.edu/cadence-0910/IC610/doc/abstract/appD.html I solved ABS-218 thanks to it :

;********************************
; CONSTRAINT GROUPS
;********************************
constraintGroups(

;( group [override] )
;( ----- ---------- )
( "LEFDefaultRouteSpec" nil "LEFDefaultRouteSpec"

interconnect(
( validLayers (AP CB M7Z VIA6Z M6Z VIA5Z M5X VIA4X M4X VIA3X M3X VIA2X M2X VIA1X M1 CO PO ) )
( validVias (M1_NW M1__NW M2X_M1_via M2X_M1_V_via M3X_M2X_via M3X_M2X_H_via M4X_M3X_via M4X_M3X_V_via M5X_M4X_via M5X_M4X_H_via M6Z_M5X_via M6Z_M5X_V_via M7Z_M6Z_via M7Z_M6Z_H_via AP_M7Z_via M1_POLYP M1_POLYN PTAP NTAP M1_POD M1_NOD M1__PO M1__PO_H M1_OD M1_PO M1_PO_H M2X_M1 M2X_M1_V M3X_M2X M3X_M2X_H M4X_M3X M4X_M3X_V M5X_M4X M5X_M4X_H M6Z_M5X M6Z_M5X_V M7Z_M6Z M7Z_M6Z_H AP_M7Z FI_AP ) )
) ;interconnect
) ;LEFDefaultRouteSpec
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