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Abstract Generator : abstract view with just "M1 net layer" => instead of "M1 drawing" and "M1 pin layers"

samung

Hi !!

I managed to get an Abstract view of my simple inverter cell, from a layout.oa view (up to M1 layer). See attachment.

However, in this Abstract view, i just have one layer : M1 net. Actually I would like to have "M1 drawing" and "M1 pin" layers + the contact "CO layer" to see the pins (vdd/vss/A/Y) in the viewer and the contacts.

In my layout.oa input file, my strategy for the pin definition is:  

one layer or M1 drawing with connectivity vdd

+ layer pin M1 on this layer (Terminal Name : vdd)

+ layer text drawing "vdd" (no connectivity) 

 

I think, I have to do something "Step Extract" at Signal & Power panels but I cannot do what I want. I tried different combination with no sucess.

 

Thanks for any help !!

 

P. 

StdCell_Abstract_Layers_layout_to_LEF.pdf
Parents
  • samung

    Hi Colin,

     

    thanks for the quick reply (again) :)

    With the current setting (Pin purpose name : net and no COnstraint group defined in the File -> General options panel), it happens that I can have a correct enough (visual check) LEF view of my simple inverter cell to be able to generate a  correct enough (visual check) FRAM view (layer M1 terminal for the blockage, and the ports : vdd/vss/A/Y) (with Synopsys milkyway). I have to to the Verify Step with the Abstract Generator tool.

     

     

    • Without the typo :

     

    My strategy for the pin definition in this layout.oa :  

    one layer on M1 drawing with connectivity vdd

    + layer pin M1 on this layer (Terminal Name : vdd)

    + layer text drawing "vdd" (no connectivity) 

     

     

     

    • I have already the CO layer as valid layer :

     

     

    Extract of the tech file :

    ;********************************

    ; CONSTRAINT GROUPS

    ;********************************

    constraintGroups(

     

     ;( group [override] )

     ;( ----- ---------- )

      ( "LEFDefaultRouteSpec" nil    "LEFDefaultRouteSpec"

     

        interconnect(

         ( validLayers   (AP  CB  M7Z  VIA6Z  M6Z  VIA5Z  M5X  VIA4X  M4X  VIA3X  M3X  VIA2X  M2X  VIA1X  M1  CO  PO  ) )

         ( validVias     (M1_NW  M1__NW  M2X_M1_via  M2X_M1_V_via  M3X_M2X_via  M3X_M2X_H_via  M4X_M3X_via  M4X_M3X_V_via  M5X_M4X_via  M5X_M4X_H_via  M6Z_M5X_via  M6Z_M5X_V_via  M7Z_M6Z_via  M7Z_M6Z_H_via  AP_M7Z_via  M1_POLYP  M1_POLYN  PTAP  NTAP  M1_POD  M1_NOD  M1__PO  M1__PO_H  M1_OD  M1_PO  M1_PO_H  M2X_M1  M2X_M1_V  M3X_M2X  M3X_M2X_H  M4X_M3X  M4X_M3X_V  M5X_M4X  M5X_M4X_H  M6Z_M5X  M6Z_M5X_V  M7Z_M6Z  M7Z_M6Z_H  AP_M7Z  FI_AP  ) )

        ) ;interconnect

     

        routingGrids(

         ( verticalPitch              "M1"   0.14 )

         ( horizontalPitch            "M1"   0.14 )

         ( horizontalOffset           "M1"   0.0 )

         ( verticalOffset             "M1"   0.0 )

         ( verticalPitch              "M2X"   0.18 )

         ( horizontalPitch            "M2X"   0.18 )

         ( horizontalOffset           "M2X"   0.0 )

         ( verticalOffset             "M2X"   0.0 )

         ( verticalPitch              "M3X"   0.14 )

         ( horizontalPitch            "M3X"   0.14 )

         ( horizontalOffset           "M3X"   0.0 )

         ( verticalOffset             "M3X"   0.0 )

         ( verticalPitch              "M4X"   0.14 )

         ( horizontalPitch            "M4X"   0.14 )

         ( horizontalOffset           "M4X"   0.0 )

         ( verticalOffset             "M4X"   0.0 )

         ( verticalPitch              "M5X"   0.14 )

         ( horizontalPitch            "M5X"   0.14 )

         ( horizontalOffset           "M5X"   0.0 )

         ( verticalOffset             "M5X"   0.0 )

         ( verticalPitch              "M6Z"   0.84 )

         ( horizontalPitch            "M6Z"   0.84 )

         ( horizontalOffset           "M6Z"   0.0 )

         ( verticalOffset             "M6Z"   0.0 )

         ( verticalPitch              "M7Z"   0.84 )

         ( horizontalPitch            "M7Z"   0.84 )

         ( horizontalOffset           "M7Z"   0.0 )

         ( verticalOffset             "M7Z"   0.0 )

         ( verticalPitch              "AP"   5.0 )

         ( horizontalPitch            "AP"   5.0 )

         ( horizontalOffset           "AP"   0.0 )

         ( verticalOffset             "AP"   0.0 )

        ) ;routingGrids

     

      ) ;LEFDefaultRouteSpec 

     

     

    P. 

Reply
  • samung

    Hi Colin,

     

    thanks for the quick reply (again) :)

    With the current setting (Pin purpose name : net and no COnstraint group defined in the File -> General options panel), it happens that I can have a correct enough (visual check) LEF view of my simple inverter cell to be able to generate a  correct enough (visual check) FRAM view (layer M1 terminal for the blockage, and the ports : vdd/vss/A/Y) (with Synopsys milkyway). I have to to the Verify Step with the Abstract Generator tool.

     

     

    • Without the typo :

     

    My strategy for the pin definition in this layout.oa :  

    one layer on M1 drawing with connectivity vdd

    + layer pin M1 on this layer (Terminal Name : vdd)

    + layer text drawing "vdd" (no connectivity) 

     

     

     

    • I have already the CO layer as valid layer :

     

     

    Extract of the tech file :

    ;********************************

    ; CONSTRAINT GROUPS

    ;********************************

    constraintGroups(

     

     ;( group [override] )

     ;( ----- ---------- )

      ( "LEFDefaultRouteSpec" nil    "LEFDefaultRouteSpec"

     

        interconnect(

         ( validLayers   (AP  CB  M7Z  VIA6Z  M6Z  VIA5Z  M5X  VIA4X  M4X  VIA3X  M3X  VIA2X  M2X  VIA1X  M1  CO  PO  ) )

         ( validVias     (M1_NW  M1__NW  M2X_M1_via  M2X_M1_V_via  M3X_M2X_via  M3X_M2X_H_via  M4X_M3X_via  M4X_M3X_V_via  M5X_M4X_via  M5X_M4X_H_via  M6Z_M5X_via  M6Z_M5X_V_via  M7Z_M6Z_via  M7Z_M6Z_H_via  AP_M7Z_via  M1_POLYP  M1_POLYN  PTAP  NTAP  M1_POD  M1_NOD  M1__PO  M1__PO_H  M1_OD  M1_PO  M1_PO_H  M2X_M1  M2X_M1_V  M3X_M2X  M3X_M2X_H  M4X_M3X  M4X_M3X_V  M5X_M4X  M5X_M4X_H  M6Z_M5X  M6Z_M5X_V  M7Z_M6Z  M7Z_M6Z_H  AP_M7Z  FI_AP  ) )

        ) ;interconnect

     

        routingGrids(

         ( verticalPitch              "M1"   0.14 )

         ( horizontalPitch            "M1"   0.14 )

         ( horizontalOffset           "M1"   0.0 )

         ( verticalOffset             "M1"   0.0 )

         ( verticalPitch              "M2X"   0.18 )

         ( horizontalPitch            "M2X"   0.18 )

         ( horizontalOffset           "M2X"   0.0 )

         ( verticalOffset             "M2X"   0.0 )

         ( verticalPitch              "M3X"   0.14 )

         ( horizontalPitch            "M3X"   0.14 )

         ( horizontalOffset           "M3X"   0.0 )

         ( verticalOffset             "M3X"   0.0 )

         ( verticalPitch              "M4X"   0.14 )

         ( horizontalPitch            "M4X"   0.14 )

         ( horizontalOffset           "M4X"   0.0 )

         ( verticalOffset             "M4X"   0.0 )

         ( verticalPitch              "M5X"   0.14 )

         ( horizontalPitch            "M5X"   0.14 )

         ( horizontalOffset           "M5X"   0.0 )

         ( verticalOffset             "M5X"   0.0 )

         ( verticalPitch              "M6Z"   0.84 )

         ( horizontalPitch            "M6Z"   0.84 )

         ( horizontalOffset           "M6Z"   0.0 )

         ( verticalOffset             "M6Z"   0.0 )

         ( verticalPitch              "M7Z"   0.84 )

         ( horizontalPitch            "M7Z"   0.84 )

         ( horizontalOffset           "M7Z"   0.0 )

         ( verticalOffset             "M7Z"   0.0 )

         ( verticalPitch              "AP"   5.0 )

         ( horizontalPitch            "AP"   5.0 )

         ( horizontalOffset           "AP"   0.0 )

         ( verticalOffset             "AP"   0.0 )

        ) ;routingGrids

     

      ) ;LEFDefaultRouteSpec 

     

     

    P. 

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