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Is the device capacitance bias-dependent or independent?

Alex Liao
Hi, I would like to know if the device intrinsic capacitance like Cgs bias-dependent or independent. Giving say, bias 400mV or 500mV (common source circuit with Vgs = 400mV or 500mV) for 65nm technology, is the Cgs the same or different and why？

Thanks,
Alex
Parents

  •  Hi Alex,

     >  I got the first paragraph.

    Great!

     

    >  By saying routing capacitance, are you saying interconnection Cap between devices or the interconnection Cap inside a device?

    I was not referring to the interconnect parasitics between devices as being the voltage invariant portion of device reactance. However,  I think you've got the concept. There are contacts and small amounts of metal that connect to the physical gate (2 um x 100 um area in your example) that are sometimes referred to as "local interconnect". These parasitics will not show a voltage dependency, but are important as they set the performance of the device. Some vendors PDK will add a set of discrete resistors or capacitors outside the BSIM model to include estimates of these in a pre-layout based netlist. When simulating using a post-layout netlist, the added "local interconnect" components are not requried as the parasitic elements associated with the local interconnect will be derived from the actual layout.

    I hope this makes sense Alex!

    Shawn

Reply

  •  Hi Alex,

     >  I got the first paragraph.

    Great!

     

    >  By saying routing capacitance, are you saying interconnection Cap between devices or the interconnection Cap inside a device?

    I was not referring to the interconnect parasitics between devices as being the voltage invariant portion of device reactance. However,  I think you've got the concept. There are contacts and small amounts of metal that connect to the physical gate (2 um x 100 um area in your example) that are sometimes referred to as "local interconnect". These parasitics will not show a voltage dependency, but are important as they set the performance of the device. Some vendors PDK will add a set of discrete resistors or capacitors outside the BSIM model to include estimates of these in a pre-layout based netlist. When simulating using a post-layout netlist, the added "local interconnect" components are not requried as the parasitic elements associated with the local interconnect will be derived from the actual layout.

    I hope this makes sense Alex!

    Shawn

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