Is the device capacitance bias-dependent or independent?

Dear Alex,

 Yes,  the device intrinsic capacitance Cgs is bias-dependent. Intuitively, the gate source capacitance is a function of how depleted the channel is. As such, more or less charge is exposed as the gate source voltage is varied and hence the capacitance is a function of the DC operating point. 

However, since the specific point in the MOS structure at which the "gate" starts and the interconnect to the "gate" ends, there is also a bias voltage independent capacitance that will be due to routing capacitance to the point where the "gate" starts.

I hope this helps Alex,

Shawn 

Hi Shawn,

 I got the first paragraph.

I am interested in your saying in the second paragraph. By saying routing capacitance, are you saying interconnection Cap between devices or the interconnection Cap inside a device? By knowing the answer of this question, I would know more clearly the "start point of ‘gate’ ".

For example, I have a device nch with NF =1, W = 2u, L = 100n. Consider a real layout. 

In layout view, are you considering the total 2u * 100n poly area as a whole as the 'start point of gate' or any small squares/ number of contacts in that area as the 'start point of gate'?

If it is the former case, interconnect would be any routing to this whole poly gate. IF it is the latter case, interconnect might be referring to the one from two parts. 1.Other remaining part of 2u*100n area to those contacts or only one contact. PLUS 2. routing interconnect  outside this example device.

Thanks,

Alex 

 Hi Alex,

 >  I got the first paragraph.

Great!

>  By saying routing capacitance, are you saying interconnection Cap between devices or the interconnection Cap inside a device?

I was not referring to the interconnect parasitics between devices as being the voltage invariant portion of device reactance. However,  I think you've got the concept. There are contacts and small amounts of metal that connect to the physical gate (2 um x 100 um area in your example) that are sometimes referred to as "local interconnect". These parasitics will not show a voltage dependency, but are important as they set the performance of the device. Some vendors PDK will add a set of discrete resistors or capacitors outside the BSIM model to include estimates of these in a pre-layout based netlist. When simulating using a post-layout netlist, the added "local interconnect" components are not requried as the parasitic elements associated with the local interconnect will be derived from the actual layout.

I hope this makes sense Alex!

Shawn

Hi Shawn,

I have got all and I like your way of putting it.

Now I have another question which is partially related this topic but arose from your answer.

When I perform a DC analysis using Cadence Spectre, I can print the DC OP information. It gives me a lot of capacitances like Cgs, Cds, Cgg and so on. I have checked the spectre Manual and the equations acquiring those capacitances. They are something like this: for instance, Cgs = d Q_s / d Vgs .

It appears to me that they are doing a numerical way of measurement and the simulation is thought to be very accurate than any manual calculations.

So my question comes here:

 If considering interpreting the Cgs from simulation result in a equivalent way, can I say this as follows?

Cgs values results from three portions, 1. voltage variant portion inside the device, 2. ‘local interconnect’ 3. routing interconnect among devices. Portion 2 and 3 are layout-dependent and fixed; Portion 3 maybe involved in 1 through affecting the nodes(g d s b) voltage.

If this is not the case what is your interpretation on Capacitance from Spectre Simulation like Cgs. 

Thanks,

Alex 

Hi Alex,

 >  I have got all 

Excellent!

> If this is not the case what is your interpretation on Capacitance from Spectre Simulation like Cgs. 

 My understand, Alex, is that the values of capacitance reported by Spectre are those of the BSIM model only and do not include any capacitances associated with the local interconnect or those due to routes to nearby components. The reason I believe this is the case is that when a netlist is created using the layout derived extracted view, all of the local interconnect capacitances and routing capacitances to neighboring devices are modeled by fixed capacitors all of which are external to the BSIM model capacitances cgs, cgd, etc... Therefore, Spectre must rely on just the BSIM model when computing the partial derivatives of charge to determine the operating point capacitances.

What do you (or others) think Alex?

Shawn 

Hi Shawn,

 I understand your thoughts. 

Initially, I thought the way you did. But later, when I think of the partial derivatives of charges I have developed another idea. Even the Spectre only relies on the BSIM model, the interconnect parasitic (Res. & Cap.) from routing or local interconnect may affect the nodes voltage such as Vgs. This might change the operating state of devices and thus the result of those operating point capacitances, Cgs and others.

What do you think on this analysis?

Thanks,

Alex