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passing CDF parameters to verilog block in SpectreVerilog simulations

RomeshNandwana

I am trying to run a SpectreVerilog cosimulation with a simple analog and digital clock generator block. I am trying to pass some parameter values ("delay" for the clock generator ) to the verilog block. While it shows my parameters as CDF parameters on the symbol but it does not pass to the verilog code and uses the default value. Is there some easy way to pass the cdf parameter to this verilog block ???

Code for my verilog code is the following : 

module clock(clk );
    output clk;
      reg  clk;
    parameter delay=10;
 
  initial     //initialize the clock 
    begin
          clk = 0;        
    end
 

always #delay clk<= ~clk;   // default clock  period = 20 time units

endmodule

 

Parents
  • skillUser

    I just tested it, by the way, here's an example result after setting the instance CDF parameter to 15:

    // Library - testLib, Cell - clockTest, View - schematic
// LAST TIME SAVED: May  8 15:51:59 2014
// NETLIST TIME: May  8 15:52:09 2014
`timescale 1ns / 1ns 

module clockTest (  );


specify 
    specparam CDS_LIBNAME  = "testLib";
    specparam CDS_CELLNAME = "clockTest";
    specparam CDS_VIEWNAME = "schematic";
endspecify

clock I0 ( net1);
defparam
    I0.delay =  15;

endmodule
Reply
  • skillUser

    I just tested it, by the way, here's an example result after setting the instance CDF parameter to 15:

    // Library - testLib, Cell - clockTest, View - schematic
// LAST TIME SAVED: May  8 15:51:59 2014
// NETLIST TIME: May  8 15:52:09 2014
`timescale 1ns / 1ns 

module clockTest (  );


specify 
    specparam CDS_LIBNAME  = "testLib";
    specparam CDS_CELLNAME = "clockTest";
    specparam CDS_VIEWNAME = "schematic";
endspecify

clock I0 ( net1);
defparam
    I0.delay =  15;

endmodule
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