Stats

  • Locked Locked
  • Replies 5
  • Subscribers 125
  • Views 16279
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

passing CDF parameters to verilog block in SpectreVerilog simulations

RomeshNandwana

I am trying to run a SpectreVerilog cosimulation with a simple analog and digital clock generator block. I am trying to pass some parameter values ("delay" for the clock generator ) to the verilog block. While it shows my parameters as CDF parameters on the symbol but it does not pass to the verilog code and uses the default value. Is there some easy way to pass the cdf parameter to this verilog block ???

Code for my verilog code is the following : 

module clock(clk );
    output clk;
      reg  clk;
    parameter delay=10;
 
  initial     //initialize the clock 
    begin
          clk = 0;        
    end
 

always #delay clk<= ~clk;   // default clock  period = 20 time units

endmodule

 

  • skillUser

    Hi,

    I think you might want to look at Solution Article 1844335 for an example of how to print CDF parameters in the Verilog netlist (as defparam statements).

    Hope this helps.

    Lawrence.

  • skillUser

    I just tested it, by the way, here's an example result after setting the instance CDF parameter to 15:

    // Library - testLib, Cell - clockTest, View - schematic
// LAST TIME SAVED: May  8 15:51:59 2014
// NETLIST TIME: May  8 15:52:09 2014
`timescale 1ns / 1ns 

module clockTest (  );


specify 
    specparam CDS_LIBNAME  = "testLib";
    specparam CDS_CELLNAME = "clockTest";
    specparam CDS_VIEWNAME = "schematic";
endspecify

clock I0 ( net1);
defparam
    I0.delay =  15;

endmodule
  • RomeshNandwana

     Thanks skillUser,

    I tried it and it works fine for me too. I thought there might be a way similar to AMS simulations where the tool picks up the CDF parameters directly from the file and we dont need to do any manual edit.

     

  • Andrew Beckett

    Unfortunately not. The Verilog netlister is a non-CDF based netlister. There are enhancement requests however to make this much more straightforward. 

    That said, spectreVerilog is really obsolete and you should be using AMS instead.

    Andrew  

  • RomeshNandwana

     Thanks for the information Andrew.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.