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passing CDF parameters to verilog block in SpectreVerilog simulations

RomeshNandwana

I am trying to run a SpectreVerilog cosimulation with a simple analog and digital clock generator block. I am trying to pass some parameter values ("delay" for the clock generator ) to the verilog block. While it shows my parameters as CDF parameters on the symbol but it does not pass to the verilog code and uses the default value. Is there some easy way to pass the cdf parameter to this verilog block ???

Code for my verilog code is the following : 

module clock(clk );
    output clk;
      reg  clk;
    parameter delay=10;
 
  initial     //initialize the clock 
    begin
          clk = 0;        
    end
 

always #delay clk<= ~clk;   // default clock  period = 20 time units

endmodule

 

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  • Andrew Beckett

    Unfortunately not. The Verilog netlister is a non-CDF based netlister. There are enhancement requests however to make this much more straightforward. 

    That said, spectreVerilog is really obsolete and you should be using AMS instead.

    Andrew  

Reply
  • Andrew Beckett

    Unfortunately not. The Verilog netlister is a non-CDF based netlister. There are enhancement requests however to make this much more straightforward. 

    That said, spectreVerilog is really obsolete and you should be using AMS instead.

    Andrew  

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