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cdlIn problems

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Hello,

I am trying to use the cdlIn function to import an existing cdl netlist and create a schematic.  While I was successful in getting a simple inverter to generate, when I try to import a 3 input and gate, the tool creates a multipage schematic.  It seems as if the tool cannot handle more than 2 fets per sheet.  The and gate is composed of simple primitives (8 fets).

Also, the cdlIn was not straightforward.  Even though I have my libraries attached to an existing techlib, cdlIn would not recognize the primitives within the PDK library.  I had to copy all my nfet and pfet symbols to my working directory and call them pmos and nmos, otherwise the tool created a generic symbol called mos with an empty schematic and created an empty top level schematic with ports, but no fets.

I am using version 5.1.41 on a Linux box.

Thanks,

Chris


Originally posted in cdnusers.org by csprice63
Parents

  • Hi,

    I just tried to run cdlIn again without specifying a device map file.  Using a schematic called "and3", here are the steps I took:

    1) Created an "and3" schematic using pmos4 and nmos4 fets from analogLib.  It has 3 input ports (A, B and C), one output port (Y), a bidirectional power port (VDD) and a bidirectional ground port (VSS).  I tied all the backgates to their respective power and ground rails so that all 4 ports for the primitives were used.
    2) Ran Export->CDL
    3) Ran Import->CDL, using a new input library so I didn't clobber my old schematic.  I did not use a device map file.  I did use analogLib as my reference library, since that is what I pulled the fets from originally.

    One of the log files (ni.log or nino.log...I can't remember which one) notes that the tool could not find the fets in any library and finally says "Bingo! mos->symbol found".  They are listed as PM and NM in the cdl netlist, exactly as cdl out wrote it.  There is no top level "and3" schematic generated.  Only a "mos" symbol was generated in my working input library and it is a stub (4 ports).  It does not matter if I change the names of the fets in the CDL netlist to pmos4/nmos4 or pfet/nfet.  The results are the same.  If I delete the "mos" cell, it regenerates.  If I enable "skip primitives", I get an empty schematic with just ports.

    I also tried using OA with its SpiceIn feature.  Unfortunately, we don't have the license for that, so I'm stuck with 5.1.41.

    Chris


    Originally posted in cdnusers.org by csprice63
Reply

  • Hi,

    I just tried to run cdlIn again without specifying a device map file.  Using a schematic called "and3", here are the steps I took:

    1) Created an "and3" schematic using pmos4 and nmos4 fets from analogLib.  It has 3 input ports (A, B and C), one output port (Y), a bidirectional power port (VDD) and a bidirectional ground port (VSS).  I tied all the backgates to their respective power and ground rails so that all 4 ports for the primitives were used.
    2) Ran Export->CDL
    3) Ran Import->CDL, using a new input library so I didn't clobber my old schematic.  I did not use a device map file.  I did use analogLib as my reference library, since that is what I pulled the fets from originally.

    One of the log files (ni.log or nino.log...I can't remember which one) notes that the tool could not find the fets in any library and finally says "Bingo! mos->symbol found".  They are listed as PM and NM in the cdl netlist, exactly as cdl out wrote it.  There is no top level "and3" schematic generated.  Only a "mos" symbol was generated in my working input library and it is a stub (4 ports).  It does not matter if I change the names of the fets in the CDL netlist to pmos4/nmos4 or pfet/nfet.  The results are the same.  If I delete the "mos" cell, it regenerates.  If I enable "skip primitives", I get an empty schematic with just ports.

    I also tried using OA with its SpiceIn feature.  Unfortunately, we don't have the license for that, so I'm stuck with 5.1.41.

    Chris


    Originally posted in cdnusers.org by csprice63
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