cdlIn problems

Chris,

I am finding it a bit strange that:
1. It is creating multisheet, it should not.
2. Naming them pmos and nmos, not required unless you are using a device map file.

Try cdlin again after deleting mos cell in your import lib.
1. In the "reference library list" field specify the lib name which has nfet and pfet.
2. Don't specify device map file unless you are doing some property matching stuff.

Import again.

Thanks,
RR

Hi RR,

If I just specify the reference library (analogLib for instance) and have no device map file, the schematic ends up empty, with no components and just ports.  Are you saying run the cdlIn once with the primitives not skipped, so that it creates that "mos" device in my working library, then delete it, skip primitives and try cdlIn again?  If I don't have the "skip primitive" box checked, I don't get a top level schematic.

BTW, the analogLib that I'm using has no pfet or nfet.  It has pmos, pmos4, nmos and nmos4, so I think I have to have a device map.  It can't seem to find the fets otherwise.

Thanks,

Chris

Hi,

I just tried to run cdlIn again without specifying a device map file.  Using a schematic called "and3", here are the steps I took:

1) Created an "and3" schematic using pmos4 and nmos4 fets from analogLib.  It has 3 input ports (A, B and C), one output port (Y), a bidirectional power port (VDD) and a bidirectional ground port (VSS).  I tied all the backgates to their respective power and ground rails so that all 4 ports for the primitives were used.
2) Ran Export->CDL
3) Ran Import->CDL, using a new input library so I didn't clobber my old schematic.  I did not use a device map file.  I did use analogLib as my reference library, since that is what I pulled the fets from originally.

One of the log files (ni.log or nino.log...I can't remember which one) notes that the tool could not find the fets in any library and finally says "Bingo! mos->symbol found".  They are listed as PM and NM in the cdl netlist, exactly as cdl out wrote it.  There is no top level "and3" schematic generated.  Only a "mos" symbol was generated in my working input library and it is a stub (4 ports).  It does not matter if I change the names of the fets in the CDL netlist to pmos4/nmos4 or pfet/nfet.  The results are the same.  If I delete the "mos" cell, it regenerates.  If I enable "skip primitives", I get an empty schematic with just ports.

I also tried using OA with its SpiceIn feature.  Unfortunately, we don't have the license for that, so I'm stuck with 5.1.41.

Chris

This one should work with device map file as below:

devMap := nfet nmos4
propMatch := subtype n3

devMap := pfet pch_33
propMatch := subtype p3


Note that n3 and p3 are the models in the propMatch line. By model I mean following in a netlist:
M_0 VDDESD NET_0 VSSESD VSSESD p3 W=33U L=0.13U

For pmos devices model in netlist should have p* and for nmos device it has to be n* in the netlist. If this is not the case, you would need to modify the netlist you are importing.

In the reflib you must specify analogLib.

Make sure the import lib is empty. mos is not needed at all. mos gets created only if correct mapping is not found in reflib and that is an indication that things went wrong.

RR

Hi,

This is what I had in my device map file when I got the multi-page schematics:

devMap := nfet nmos4
propMatch := subtype NM
devMap := pfet pmos4
propMatch := subtype PM

The NM and PM are in the CDL netlist like such:

.subckt and3 A B C VDD VSS Y
*.PININFO A:In B:In C:In Y:Out VDD:B VSS:B
MP0 vdd A Y vdd PM w=2u l=0.18u
MP1 vdd B Y vdd PM w=2u l=0.18u
MP2 vdd C Y vdd PM w=2u l=0.18u
MN0 net1 A Y vss NM w=1u l=0.18u
MN1 net2 B net1 vss NM w=1u l=0.18u
MN2 vss C net2 vss NM w=1u l=0.18u
.ends

I got a warning saying the propMatch items were more than 2 characters long.  My library was empty when I started.  I also called out my reference library to be analogLib.

I got an empty schematic when I DIDN'T use the device map file.

When I look in the Cadence docs, it appears that I'm doing things correctly...it just doesn't turn out that way.  I can't find anything in SourceLink that helps.

Chris

Oops...forgot to type in the final inverter for the and3...what I typed is a nand3 of course :-).

Chris

On the "Schematic Generation" form check the value of "Maximum number of rows" and "Maximum number of Columns". Keep the values high in this field. Make it 1024. If it still creates, let me know:

What is the behavior of tool if you create a new schematic using menus? Does it creates multisheet? Or, it is happening only in case of cdl import? Which version is this (icfb -W)?

The settings you describe are the default.  I also set the density to maximum (100).  I still get multipage schematics.  I have never had problems creating schematics from scratch.  It is only a cdl in problem.  I have no problem with cdl out, no problems with simulation, no problems with layout, no problems with stream in, no problems with stream out.

Chris

I would suggest that you file a Service Request with Cadence and get it resolved with help of some AE. The AE might want to look at your display to see whats going on. Because, I have tried your exact netlist and I don't see any multisheet being created. I have used iC5141USR5 and latest ISR of IC5141 without any issues.

RR

Oh and I forgot...it's IC5141/USR3