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cdlIn problems

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Hello,

I am trying to use the cdlIn function to import an existing cdl netlist and create a schematic.  While I was successful in getting a simple inverter to generate, when I try to import a 3 input and gate, the tool creates a multipage schematic.  It seems as if the tool cannot handle more than 2 fets per sheet.  The and gate is composed of simple primitives (8 fets).

Also, the cdlIn was not straightforward.  Even though I have my libraries attached to an existing techlib, cdlIn would not recognize the primitives within the PDK library.  I had to copy all my nfet and pfet symbols to my working directory and call them pmos and nmos, otherwise the tool created a generic symbol called mos with an empty schematic and created an empty top level schematic with ports, but no fets.

I am using version 5.1.41 on a Linux box.

Thanks,

Chris


Originally posted in cdnusers.org by csprice63
Parents

  • Hi,

    This is what I had in my device map file when I got the multi-page schematics:

    devMap := nfet nmos4
    propMatch := subtype NM
    devMap := pfet pmos4
    propMatch := subtype PM

    The NM and PM are in the CDL netlist like such:

    .subckt and3 A B C VDD VSS Y
    *.PININFO A:In B:In C:In Y:Out VDD:B VSS:B
    MP0 vdd A Y vdd PM w=2u l=0.18u
    MP1 vdd B Y vdd PM w=2u l=0.18u
    MP2 vdd C Y vdd PM w=2u l=0.18u
    MN0 net1 A Y vss NM w=1u l=0.18u
    MN1 net2 B net1 vss NM w=1u l=0.18u
    MN2 vss C net2 vss NM w=1u l=0.18u
    .ends

    I got a warning saying the propMatch items were more than 2 characters long.  My library was empty when I started.  I also called out my reference library to be analogLib.

    I got an empty schematic when I DIDN'T use the device map file.

    When I look in the Cadence docs, it appears that I'm doing things correctly...it just doesn't turn out that way.  I can't find anything in SourceLink that helps.

    Chris


    Originally posted in cdnusers.org by csprice63
Reply

  • Hi,

    This is what I had in my device map file when I got the multi-page schematics:

    devMap := nfet nmos4
    propMatch := subtype NM
    devMap := pfet pmos4
    propMatch := subtype PM

    The NM and PM are in the CDL netlist like such:

    .subckt and3 A B C VDD VSS Y
    *.PININFO A:In B:In C:In Y:Out VDD:B VSS:B
    MP0 vdd A Y vdd PM w=2u l=0.18u
    MP1 vdd B Y vdd PM w=2u l=0.18u
    MP2 vdd C Y vdd PM w=2u l=0.18u
    MN0 net1 A Y vss NM w=1u l=0.18u
    MN1 net2 B net1 vss NM w=1u l=0.18u
    MN2 vss C net2 vss NM w=1u l=0.18u
    .ends

    I got a warning saying the propMatch items were more than 2 characters long.  My library was empty when I started.  I also called out my reference library to be analogLib.

    I got an empty schematic when I DIDN'T use the device map file.

    When I look in the Cadence docs, it appears that I'm doing things correctly...it just doesn't turn out that way.  I can't find anything in SourceLink that helps.

    Chris


    Originally posted in cdnusers.org by csprice63
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