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cdlIn problems

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Hello,

I am trying to use the cdlIn function to import an existing cdl netlist and create a schematic.  While I was successful in getting a simple inverter to generate, when I try to import a 3 input and gate, the tool creates a multipage schematic.  It seems as if the tool cannot handle more than 2 fets per sheet.  The and gate is composed of simple primitives (8 fets).

Also, the cdlIn was not straightforward.  Even though I have my libraries attached to an existing techlib, cdlIn would not recognize the primitives within the PDK library.  I had to copy all my nfet and pfet symbols to my working directory and call them pmos and nmos, otherwise the tool created a generic symbol called mos with an empty schematic and created an empty top level schematic with ports, but no fets.

I am using version 5.1.41 on a Linux box.

Thanks,

Chris


Originally posted in cdnusers.org by csprice63
Parents

  • This one should work with device map file as below:

    devMap := nfet nmos4
    propMatch := subtype n3

    devMap := pfet pch_33
    propMatch := subtype p3


    Note that n3 and p3 are the models in the propMatch line. By model I mean following in a netlist:
    M_0 VDDESD NET_0 VSSESD VSSESD p3 W=33U L=0.13U

    For pmos devices model in netlist should have p* and for nmos device it has to be n* in the netlist. If this is not the case, you would need to modify the netlist you are importing.

    In the reflib you must specify analogLib.

    Make sure the import lib is empty. mos is not needed at all. mos gets created only if correct mapping is not found in reflib and that is an indication that things went wrong.

    RR


    Originally posted in cdnusers.org by rairaj
Reply

  • This one should work with device map file as below:

    devMap := nfet nmos4
    propMatch := subtype n3

    devMap := pfet pch_33
    propMatch := subtype p3


    Note that n3 and p3 are the models in the propMatch line. By model I mean following in a netlist:
    M_0 VDDESD NET_0 VSSESD VSSESD p3 W=33U L=0.13U

    For pmos devices model in netlist should have p* and for nmos device it has to be n* in the netlist. If this is not the case, you would need to modify the netlist you are importing.

    In the reflib you must specify analogLib.

    Make sure the import lib is empty. mos is not needed at all. mos gets created only if correct mapping is not found in reflib and that is an indication that things went wrong.

    RR


    Originally posted in cdnusers.org by rairaj
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