cdlIn problems

Hello,

I am trying to use the cdlIn function to import an existing cdl netlist and create a schematic.  While I was successful in getting a simple inverter to generate, when I try to import a 3 input and gate, the tool creates a multipage schematic.  It seems as if the tool cannot handle more than 2 fets per sheet.  The and gate is composed of simple primitives (8 fets).

Also, the cdlIn was not straightforward.  Even though I have my libraries attached to an existing techlib, cdlIn would not recognize the primitives within the PDK library.  I had to copy all my nfet and pfet symbols to my working directory and call them pmos and nmos, otherwise the tool created a generic symbol called mos with an empty schematic and created an empty top level schematic with ports, but no fets.

I am using version 5.1.41 on a Linux box.

Thanks,

Chris