ADExl problem with bus notation

Running a spectre simulation from adexl I am getting this error:

Error found by spectre during circuit read-in.
    ERROR (SFE-874): "input.scs" 3633: Unexpected operator ">". Expected end of
        file or end of line.

The interesting part of scs netlist is listed below. Please note that the \ escape was applied to the netlist but not to the output signals. I don't know why.

I tried the \ escape on the "Outputs Setup" pane but then I could not check the save box. Thus, I assume I cannot enter the signals with the \ escape in the outputs setup pane. How can I getaround that problem?

IWRLINEDEC_TOP (WADR_IN_0 WADR_IN_1 WADR_IN_2 WADR_IN_3 WA0C_DEC \
        WAC_UNUSED_DEC\<0\> WAC_UNUSED_DEC\<1\> WAC_UNUSED_DEC\<2\> \
        WAC_UNUSED_DEC\<3\> WAC_UNUSED_DEC\<4\> WAC_UNUSED_DEC\<5\> \
        WAC_UNUSED_DEC\<6\> WAC_UNUSED_DEC\<7\> WAC_UNUSED_DEC\<8\> \
        WAC_UNUSED_DEC\<9\> WAC_UNUSED_DEC\<10\> WAC_UNUSED_DEC\<11\> \
        WAC_UNUSED_DEC\<12\> WAC_UNUSED_DEC\<13\> WA15C_DEC \
        WR_AC_INT_BOT_TOPADRDEC\<0\> WR_AC_INT_BOT_TOPADRDEC\<1\> \
        WR_AC_INT_BOT_TOPADRDEC\<2\> WR_AC_INT_BOT_TOPADRDEC\<3\> \
        WR_AC_INT_N_BOT_TOPADRDEC\<0\> WR_AC_INT_N_BOT_TOPADRDEC\<1\> \
        WR_AC_INT_N_BOT_TOPADRDEC\<2\> WR_AC_INT_N_BOT_TOPADRDEC\<3\> \
        RADR_IN_0 LBIST_EN_DC VDD VSS) CAB_C8T_ADRDEC16C_WR
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=85 \
    tnom=25 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf
tran tran stop=1n errpreset=moderate write="spectre.ic" \
    writefinal="spectre.fc" annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
save NCLK Ilsdrv/wwl_wwldrv_w0 Ilsdrv/wwl_wwldrv_w15 Ilsdrv/wwl_wwldrv_wN \
    Icore/RWL_B0_WN<0> Icore/RWL_BN_W0<0> Icore/RWL_B0_W0<0> \
    Icore/RWL_BN_WN<0> Icore/RWL_B0_WN<31> Icore/RWL_BN_W0<31> \
    Icore/RWL_B0_W0<31> Icore/RWL_BN_WN<31> Icore/RWL_NEAR_W0 \
    Icore/RWL_NEAR_W15 Icore/RWL_NEAR_WN Icore/WWL_B0_WN<0> \
    Icore/WWL_BN_W0<0> Icore/WWL_B0_W0<0> Icore/WWL_BN_WN<0> \
    Icore/WWL_B0_WN<31> Icore/WWL_BN_W0<31> Icore/WWL_B0_W0<31> \
    Icore/WWL_BN_WN<31> Icore/WWL_NEAR_W0 Icore/WWL_NEAR_W15 \
    Icore/WWL_NEAR_WN