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VerilogA compiler

Sali

 Dear all,

I'm using VerilogA model in my design in Cadence, I have some variables in the model that should be changed with time, actually I have two questions:

1- Is there a way to display the value of those variables during the analog simulation? I was looking for VerilogA compiler to test my code first but I didn't find, can some one suggest me a website or any information?

2- The statement of  @(initial_step), does it mean the command after it will be exceuted only one time, which is the begining of the simulation?

 

Thank you in advance,

 

Parents

  • You can use the $strobe or $display (or even $debug) task to display information during simulation. You can also use the "saveahdlvars" option on the Outputs->Save All form in ADE and then you can plot any variables versus time (you'll need to use the results browser to access them) and then you can see how they vary.

    And yes, the Initial_step means that it will execute at the beginning.

    See the VerilogA documentation (Run <MMSIMinstDir>/bin/cdnshelp to bring up the documentation, and you'll be able to find the VerilogA reference manual within that).

    Regards,

    Andrew.

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  • You can use the $strobe or $display (or even $debug) task to display information during simulation. You can also use the "saveahdlvars" option on the Outputs->Save All form in ADE and then you can plot any variables versus time (you'll need to use the results browser to access them) and then you can see how they vary.

    And yes, the Initial_step means that it will execute at the beginning.

    See the VerilogA documentation (Run <MMSIMinstDir>/bin/cdnshelp to bring up the documentation, and you'll be able to find the VerilogA reference manual within that).

    Regards,

    Andrew.

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