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VerilogA compiler

Sali
Sali over 11 years ago

 Dear all,

I'm using VerilogA model in my design in Cadence, I have some variables in the model that should be changed with time, actually I have two questions:

1- Is there a way to display the value of those variables during the analog simulation? I was looking for VerilogA compiler to test my code first but I didn't find, can some one suggest me a website or any information?

2- The statement of  @(initial_step), does it mean the command after it will be exceuted only one time, which is the begining of the simulation?

 

Thank you in advance,

 

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  • Sali
    Sali over 11 years ago

     Thank you for your help.

    It works with me now, but the question is can I use ddt and ddx to model the differential equation? I'm asking this question because ddt gave me unexpected result, I use it to test when the curve reached the stable point (becames fixed to a certain value for the rest of the simulation) so I expected the ddt to be changing until becomes zero when the curve becomes stable but it always gives me 3 althogh the curve is stable after a certain period of time?

    and is there a way to build a model in Cadence using a high level language liek C++?

    Thanks again

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  • Sali
    Sali over 11 years ago

     Thank you for your help.

    It works with me now, but the question is can I use ddt and ddx to model the differential equation? I'm asking this question because ddt gave me unexpected result, I use it to test when the curve reached the stable point (becames fixed to a certain value for the rest of the simulation) so I expected the ddt to be changing until becomes zero when the curve becomes stable but it always gives me 3 althogh the curve is stable after a certain period of time?

    and is there a way to build a model in Cadence using a high level language liek C++?

    Thanks again

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