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Extracted parameters do not match with the schematic.

jagadishdn

I am using cadence 6.1.5 and UMC 90nm technology library. I am facing a problem with large deviation of extracted parameters of the devices.

This is illustrated as follows. I have designed  a CMOS inverter with minimum sizes using the schematic composer. The same transistors are placed in the layout and RC extracted with Assura. I dc simulated both schematic and extracted inverters. However when checked the dc operating point, the parameters "cjd" and "cjs" of the transistors in schematic were in the range of 0.2fF, while for the extracted transistors it is close to 1fF.

Clearly there is a deviation in extracted parameter upto 500% than an expected 20-30% error. The netlist refer the same model file. Please suggest me to overcome this problem.

Thanks

 Jagadish

 

 

  • Hi Jagadish

    Would you please check the following?

    a. Use ADE to netlist the extracted view
    b. Check W and L of the transistors
    c. Are they correct?

    Best regards
    Quek

  • Hi Quek,

    I had followed as you suggested. The W and L for the pmos and nmos of the inverters are 240n,90n and 120n,90n, respectively, in the schematic of the inverter. The av_extracted design is selected and netlisted. The transistor sizes match. However, the dc analysis shows cjd and cjs as 1fF, which is five times more than in schematic design.

    I am attaching the netlist of av_extracted since I could not upload snapshots.

     

    // Generated for: spectre
    // Generated on: Jul 30 09:58:03 2014
    // Design library name: test
    // Design cell name: inv_erwin
    // Design view name: config
    simulator lang=spectre
    global 0
    include "/cad/tech_libs/umc_90nm/G-9FD-LOGIC_MIXED_MODE90N-1P9M-LOW_K_UMK90FDKLMC-FDK-Ver.B15_PB/Models/Spectre/L90_LL12_V102.lib.scs" section=tt

    // Library name: test
    // Cell name: inv_erwin
    // View name: av_extracted
    // Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
    c1 (vdd gnd) capacitor c=3.30533e-17
    c2 (in gnd) capacitor c=8.78635e-17
    c3 (out gnd) capacitor c=6.0132e-17
    c4 (\1\:in gnd) capacitor c=9.82822e-17
    c5 (\2\:in gnd) capacitor c=9.89674e-17
    c6 (\1\:out gnd) capacitor c=7.09875e-17
    c7 (\3\:vdd gnd) capacitor c=5.53324e-17
    c8 (\2\:out gnd) capacitor c=5.11186e-17
    c9 (\2\:vdd gnd) capacitor c=4.85956e-17
    rj1 (vdd \2\:vdd) resistor r=0.02767
    rj2 (\2\:vdd \3\:vdd) resistor r=15.5581
    rj4 (\1\:gnd \3\:gnd) resistor r=15.4065
    rj5 (\3\:gnd gnd) resistor r=0.003038
    rj7 (out \1\:out) resistor r=15.8375
    rj8 (out \2\:out) resistor r=15.548
    rk1 (\1\:in in) resistor r=118.326
    rk2 (in \2\:in) resistor r=145.889
    PM0 (\1\:out \1\:in \3\:vdd vdd) p_12_ll l=9e-08 w=2.4e-07 sa=2.8e-07 \
            sb=2.8e-07 nf=1 mis_flag=1 sd=0 as=480f ad=480f ps=4.48u pd=4.48u \
            m=1 mf=1
    PM1 (\2\:out \2\:in \1\:gnd gnd) n_12_ll l=9e-08 w=1.2e-07 sa=2.9e-07 \
            sb=2.9e-07 nf=1 mis_flag=1 sd=0 as=480f ad=480f ps=4.48u pd=4.48u \
            m=1 mf=1
    simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
        tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
        digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
        checklimitdest=psf
    dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status
    dcOpInfo info what=oppoint where=rawfile
    modelParameter info what=models where=rawfile
    element info what=inst where=rawfile
    outputParameter info what=output where=rawfile
    designParamVals info what=parameters where=rawfile
    primitives info what=primitives where=rawfile
    subckts info what=subckts  where=rawfile
    saveOptions options save=allpub

     

    Thanks

    Jagadish 

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