Extracted parameters do not match with the schematic.

I am using cadence 6.1.5 and UMC 90nm technology library. I am facing a problem with large deviation of extracted parameters of the devices.

This is illustrated as follows. I have designed  a CMOS inverter with minimum sizes using the schematic composer. The same transistors are placed in the layout and RC extracted with Assura. I dc simulated both schematic and extracted inverters. However when checked the dc operating point, the parameters "cjd" and "cjs" of the transistors in schematic were in the range of 0.2fF, while for the extracted transistors it is close to 1fF.

Clearly there is a deviation in extracted parameter upto 500% than an expected 20-30% error. The netlist refer the same model file. Please suggest me to overcome this problem.

Thanks

 Jagadish