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How to read a text file in a VerilogA code

Alifa

 Hello every body!

I will greatly appreciate your help.

In order to test a serial DAC I need to input the DAC with serial bits ( any pattern like 01110001111), one bit at a clock cycle. So my text file (bit_sequence.txt) looks like this:

 1

0

 1

0

0

1

.

.

.

Basically, I want a VerilogA model that reads "bit_sequence.txt" and output one bit at a clock cycle to my DAC circuit. I tried the following code. It compiles with no error, but I can't see the above pattern in my simulation. Moreover, after running simulation, the bit_sequence.txt gets empty! :)

module fileReader_1output(out1, clk);
input clk;
output out1;
electrical out1, clk;

parameter real vtrans = 1.0;
parameter fileName = "~/bit_sequence.txt";

integer fileHandle;
integer decimal_output;
integer captured_data;

analog begin

    @ (initial_step)
        fileHandle = $fopen(fileName);
    @ (final_step)
        $fclose(fileHandle);
    @ (cross (V(clk) - vtrans,+1)) begin
                 
        decimal_output = $fscanf(fileHandle,"%d", captured_data);
        V(out1)<= decimal_output; //captured_data;    

     end
end

endmodule

  • skillUser

    Hi Alifa,

    When you use $fopen there is a second argument for the mode - I think that the default must be write (overwrite) and so you would need to specify read mode so that you don't clobber the file contents and so that you are able to read from the file.  I have not tried your example, but you may need to adjust the pattern to cope with possible spaces in the input file (your text above shows some preceeding space on some lines).

    Hopefully the first point is the only one that you need to account for and your code works after a minor adjustment. Good luck!

    Regards,

    Lawrence.

  • Alifa

     

    Dear Lawrence,

    Thank you for the quick reply. What should I set as second argument with $fopen(fileName) to specify read mode?
    Thanks again.
    Alifa
  • skillUser

    Hi Alifa,

    I believe it would be something like this:

    $fopen(fileName, "r")

    A quick look at the documentation tells you this (and also that the default mode is indeed "w"), I didn't check earlier...

    Regards,

    Lawrence.

  • Alifa

     Yesss, thanks Lawrence ;) I tried this and the original text file is not touched. Still my code has some other problems. somewhere here when place the captured bit at the output port named "out1".

            decimal_output = $fscanf(fileHandle,"%d", captured_data);
            V(out1) <= decimal_output; //captured_data;

     

  • Alifa

    Hi Lawrence

    I fixed the problem. Thank you. Here comes the code:

     analog begin

        @ (initial_step)
            fileHandle = $fopen(fileName, "r");
        @ (final_step)
            $fclose(fileHandle);
        @ (cross (V(clk) - vtrans,+1)) begin
             decimal_output = $fscanf(fileHandle,"%d", captured_data);
             x = ( captured_data > vtrans);
                                  
        end
        
        V(out1) <+ transition( vlogic_high*x + vlogic_low*!x,tdel, trise, tfall );
    end

    endmodule

  • AishwaryaP
    Hi,
    I am facing problem in fscanf statement in verilog-A.

    fid=$fopen("results.csv","r");
    while(retval == 4) begin
    retval = $fscanf(fid, "%e,%e,%e,%e", A, B, C, D);
    $display("%e,%e,%e,%e", A, B, C, D);
    end
    A,B,C,D are all declared as real.

    results.csv contains values in this format.
    3.29E-06,1.28E+06,0.495778,1.94E-07
    3.32E-06,1.29E+06,0.4948,1.92E-07
    3.42E-06,1.33E+06,0.495651,1.87E-07

    End of line is a carriage return \r. My verilogA code reads only the first line. simulator throws the following error for second line.
    Format string in $freads/$fscanf/$sscanf does not match input file/string. Change the format string

    adding \r to $fscanf doesnt work. Please suggest me a solution.
  • Andrew Beckett

    Which simulator are you using and which version? I just took your code and added a little extra to make it complete:

    `include "disciplines.vams"

    module forum35 (a);
    output a;
    electrical a;

    real A,B,C,D;
    integer fid,retval;

    analog initial begin
      fid=$fopen("forumresults.csv","r");
      retval=4;
      while(retval == 4) begin
        retval = $fscanf(fid, "%e,%e,%e,%e", A, B, C, D);
        $display("%e,%e,%e,%e", A, B, C, D);
      end
    end

    endmodule

    It then worked fine (I changed the filename). I see:

    Reading file: /export/home/username/tools/spectre/forumresults.csv
    3.290000e-06,1.280000e+06,4.957780e-01,1.940000e-07
    3.320000e-06,1.290000e+06,4.948000e-01,1.920000e-07
    3.420000e-06,1.330000e+06,4.956510e-01,1.870000e-07
    3.420000e-06,1.330000e+06,4.956510e-01,1.870000e-07

    The last line would be a duplicate because retval would probably have been -1 for end of file (I didn't check).

    This is using Spectre16.1 - but would be a bit surprised if this is particularly fussy about the version...

    Andrew.

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