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  3. How to read a text file in a VerilogA code

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How to read a text file in a VerilogA code

Alifa
Alifa over 11 years ago

 Hello every body!

I will greatly appreciate your help.

In order to test a serial DAC I need to input the DAC with serial bits ( any pattern like 01110001111), one bit at a clock cycle. So my text file (bit_sequence.txt) looks like this:

 1

0

 1

0

0

1

.

.

.

Basically, I want a VerilogA model that reads "bit_sequence.txt" and output one bit at a clock cycle to my DAC circuit. I tried the following code. It compiles with no error, but I can't see the above pattern in my simulation. Moreover, after running simulation, the bit_sequence.txt gets empty! :)

module fileReader_1output(out1, clk);
input clk;
output out1;
electrical out1, clk;

parameter real vtrans = 1.0;
parameter fileName = "~/bit_sequence.txt";

integer fileHandle;
integer decimal_output;
integer captured_data;

analog begin

    @ (initial_step)
        fileHandle = $fopen(fileName);
    @ (final_step)
        $fclose(fileHandle);
    @ (cross (V(clk) - vtrans,+1)) begin
                 
        decimal_output = $fscanf(fileHandle,"%d", captured_data);
        V(out1)<= decimal_output; //captured_data;    

     end
end

endmodule

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  • AishwaryaP
    AishwaryaP over 8 years ago
    Hi,
    I am facing problem in fscanf statement in verilog-A.

    fid=$fopen("results.csv","r");
    while(retval == 4) begin
    retval = $fscanf(fid, "%e,%e,%e,%e", A, B, C, D);
    $display("%e,%e,%e,%e", A, B, C, D);
    end
    A,B,C,D are all declared as real.

    results.csv contains values in this format.
    3.29E-06,1.28E+06,0.495778,1.94E-07
    3.32E-06,1.29E+06,0.4948,1.92E-07
    3.42E-06,1.33E+06,0.495651,1.87E-07

    End of line is a carriage return \r. My verilogA code reads only the first line. simulator throws the following error for second line.
    Format string in $freads/$fscanf/$sscanf does not match input file/string. Change the format string

    adding \r to $fscanf doesnt work. Please suggest me a solution.
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  • AishwaryaP
    AishwaryaP over 8 years ago
    Hi,
    I am facing problem in fscanf statement in verilog-A.

    fid=$fopen("results.csv","r");
    while(retval == 4) begin
    retval = $fscanf(fid, "%e,%e,%e,%e", A, B, C, D);
    $display("%e,%e,%e,%e", A, B, C, D);
    end
    A,B,C,D are all declared as real.

    results.csv contains values in this format.
    3.29E-06,1.28E+06,0.495778,1.94E-07
    3.32E-06,1.29E+06,0.4948,1.92E-07
    3.42E-06,1.33E+06,0.495651,1.87E-07

    End of line is a carriage return \r. My verilogA code reads only the first line. simulator throws the following error for second line.
    Format string in $freads/$fscanf/$sscanf does not match input file/string. Change the format string

    adding \r to $fscanf doesnt work. Please suggest me a solution.
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