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a pll stability : phase margin and gain margin ?

Handrian

 Hi,

I designed an pll circuit. I want to check the stabilbity of system in simulation.

- In transient analyses, when I plot the control voltage, its value is constant at 10us, so it's ok !

- In stability analyses, i wanna plot the bode diagram in open loop. So for that, I broke the loop after the divider circuit. I put the Iprobe after the loop fiter. I used the Vsin source with 600mV of amplitude for the input reference.

When i plot with large band the phase margin and the gain phase, I got this graph :

 

It is nothing ! the margin phase and gain phase are not determined.

I don't understand,  What is it due ? may be the method to breal the loop ? Where I put exactly the Iprobe ? What I must enter on the Vsin source ? Did I forget something for the parameter of stability analyses ? 

 

Someone can bring a full method to measure the stability of pll ?

Thanks in advance,

Andrian

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