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  3. Configuring new PDK

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Configuring new PDK

Vishnuram
Vishnuram over 11 years ago

I was configuring the new PDK in Cadence virtuoso version IC6.1.4.500.12( one PDK is already existing in the home directory). so i make a new folder(named "new_PDK") in the home directory and added the files(cadence.cshrc, cds.lib, .cdsinit, .cdsenv, bindkeys and the PDK folder). when i source the cadence.cshrc file from from folder new_PDK, i am listing out the problems i am facing:

 

1. its shows techfile conflict

" there is a conflict in techfile graph

  Look at techfile reported error massage in CIW

  correct techfile conflict before proceeding "

 

  Whill loading the files, it takes techfile.tf, pdkutil and display.drf file from PDK folder olny.

 

2. In the schematic window, i can call the instances but unable to connect using wires(wires are not coming. rest all shortcut keys are working.

 

3. In the layer selection windows(LSW) palletes are not visible.

" (LE-101804): Cannot get valid layer form LSW window. "

 

   i can see the layer when i click on layer but again shows blank when i scroll it down.

 

4. Cadence windows crash when i try to make any layer in the layout.

"  \o (LE-101804): Cannot get valid layer form LSW window.
   \a leSetLSWBBox(list(57:328 207:1028)) "

 

Everthing working properly with the old PDK exist in home directory.

 

Please help me out.

 

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  • Quek
    Quek over 11 years ago
    Hi Vishnuram

    Would you please let us know if you have the old and new tech libraries in library manager? If yes, would removing the old tech library from cds.lib resolve the problem?

    Best regards
    Quek

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  • Vishnuram
    Vishnuram over 11 years ago

    Hi Quek,

    Thanks for the reply

    yes, i have already removed the old tech library manager from the cds.lib file.
    but problem is still there.

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  • Quek
    Quek over 11 years ago
    Hi Vishnuram

    Would you please execute the following cmds in ciw and let us know the output?

    foreach( lib ddGetLibList()
       printf("Lib: %s tech: %L\n" lib~>name setof(x lib~>files~>name x=="tech.db"))
    ) ;foreach

    Thanks
    Quek
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  • Vishnuram
    Vishnuram over 11 years ago

    Hi Quek,

    i executed those command in CIW.
    but still the same error. tech file conflict and wire problem.

    " p, li { white-space: pre-wrap; } |||||||color set to unbound, was nil

    |||color set to nil, was nil

    * Field is "color" *

    *Error* hiCreateCyclicField: value must be contained within the list of choices

    "

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  • theopaone
    theopaone over 11 years ago

    It looks like the loading of the techfile wiped out all the layers, there was a warning  in the first post about a techfile conflict. Can you post the output from the CIW to give us a clearer idea of the problem?

     

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  • Vishnuram
    Vishnuram over 11 years ago

    CIW after adding technology file to the new library named "test101" p, li { white-space: pre-wrap; }

    Loading silterraB18V/libInit.il ...

    Loading silterraB18V/loadCxt.ile ... done!

    Loading context 'silterraB18V' from library 'silterraB18V' ... done!

    Loading context 'pdkUtils' from library 'silterraB18V' ... done!

    Loading silterraB18V/display.drf ...

    done!

    Loading silterraB18V/libInitCktPro.il ... done!

    Loading silterraB18V/libInitCustomExit.il ... Initializing loadCxt.ile from libInit.il for library silterraB18V...

    function PasLoadLibContext redefined

    Initializing silterraLoadSkillDir.ile from libInit.il for library silterraB18V...

    Loading oasis.cxt

    Loading analog.cxt

    Loading asimenv.cxt

    Loading spectrei.cxt

    Loading relXpert.cxt

    Loading hspiceD.cxt

    ..........................................

    . Current PDK Configuration .

    ..........................................

    . Metal Option : 6LM

    . Top Metal : Standard

    . Mim : 1FF

    . H Poly : 1K

    . MV Option : MV

    . HV Option : B18V40

    ..........................................

    . *Note* The DC current through resistors should not exceed 1mA per um of width.

    . Above this current level, the voltage coefficients may not behave properly.

    ..........................................

    done!

    Loaded silterraB18V/libInit.il successfully!

    *WARNING* (TECH-2000178): A Default Manufacturing Grid conflict has been detected in the technology hierarchy.

    It is caused by the following list of Libraries: silterraB18V; cdsDefTechLib;

    *WARNING* (TECH-2000050): Unable to set references on tech because conflicts would result in tech silterraB18V.

    INFO (TECH-180011): Design library 'test101' successfully attached to technology library 'silterraB18V'.

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  • theopaone
    theopaone over 11 years ago

     I would suspect that this conflict is causing the problem or it may be an issue with the dbuPerUU on the viewTypes (usually the layout viewType). I don't have access to Virtuoso at this time, I'm on holiday, but check the dbuPerUU and the mfgGridResolution in both techfiles (dump the techfiles if you don't have a .tf) and post the relevant sections here.

    *WARNING* (TECH-2000178): A Default Manufacturing Grid conflict has been detected in the technology hierarchy.

    It is caused by the following list of Libraries: silterraB18V; cdsDefTechLib;

     

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  • Vishnuram
    Vishnuram over 11 years ago

    Hi Theopane,

    I have both the format of PDK(CDB and OA). Issues are resolved by converting the CDB format PDK to OA format.  Converted OA format is working properly without any conflict.

    But original OA format is still having the issues. I guess there is some issues with tech.db file. I'am still trying to figure it out.

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  • theopaone
    theopaone over 11 years ago

     It hit me like a wave in the surf here in the Gulf of Mexico off south Texas. Actually I was standing in the waves when I realized your issue.

    The technology file in OA was setup to be an inherited technology database. This means that some of the technology data was inherited from multiple libraries, including cdsTechLib. The inheritance checks for conflicting data between the libraries giving the error and stopping the load.

    *WARNING* (TECH-2000178): A Default Manufacturing Grid conflict has been detected in the technology hierarchy.

    It is caused by the following list of Libraries: silterraB18V; cdsDefTechLib;

     Your base techlibrary, silterraB18V, was either set up this way or your design library was using referencing that library rather than attaching it. Thus you had the conflict. By converting the library from CDB, you have set up an attachable library rather than the reference libs.

    Ted

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