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Configuring new PDK

Vishnuram

I was configuring the new PDK in Cadence virtuoso version IC6.1.4.500.12( one PDK is already existing in the home directory). so i make a new folder(named "new_PDK") in the home directory and added the files(cadence.cshrc, cds.lib, .cdsinit, .cdsenv, bindkeys and the PDK folder). when i source the cadence.cshrc file from from folder new_PDK, i am listing out the problems i am facing:

 

1. its shows techfile conflict

" there is a conflict in techfile graph

  Look at techfile reported error massage in CIW

  correct techfile conflict before proceeding "

 

  Whill loading the files, it takes techfile.tf, pdkutil and display.drf file from PDK folder olny.

 

2. In the schematic window, i can call the instances but unable to connect using wires(wires are not coming. rest all shortcut keys are working.

 

3. In the layer selection windows(LSW) palletes are not visible.

" (LE-101804): Cannot get valid layer form LSW window. "

 

   i can see the layer when i click on layer but again shows blank when i scroll it down.

 

4. Cadence windows crash when i try to make any layer in the layout.

"  \o (LE-101804): Cannot get valid layer form LSW window.
   \a leSetLSWBBox(list(57:328 207:1028)) "

 

Everthing working properly with the old PDK exist in home directory.

 

Please help me out.

 

Parents

  • CIW after adding technology file to the new library named "test101" p, li { white-space: pre-wrap; }

    Loading silterraB18V/libInit.il ...

    Loading silterraB18V/loadCxt.ile ... done!

    Loading context 'silterraB18V' from library 'silterraB18V' ... done!

    Loading context 'pdkUtils' from library 'silterraB18V' ... done!

    Loading silterraB18V/display.drf ...

    done!

    Loading silterraB18V/libInitCktPro.il ... done!

    Loading silterraB18V/libInitCustomExit.il ... Initializing loadCxt.ile from libInit.il for library silterraB18V...

    function PasLoadLibContext redefined

    Initializing silterraLoadSkillDir.ile from libInit.il for library silterraB18V...

    Loading oasis.cxt

    Loading analog.cxt

    Loading asimenv.cxt

    Loading spectrei.cxt

    Loading relXpert.cxt

    Loading hspiceD.cxt

    ..........................................

    . Current PDK Configuration .

    ..........................................

    . Metal Option : 6LM

    . Top Metal : Standard

    . Mim : 1FF

    . H Poly : 1K

    . MV Option : MV

    . HV Option : B18V40

    ..........................................

    . *Note* The DC current through resistors should not exceed 1mA per um of width.

    . Above this current level, the voltage coefficients may not behave properly.

    ..........................................

    done!

    Loaded silterraB18V/libInit.il successfully!

    *WARNING* (TECH-2000178): A Default Manufacturing Grid conflict has been detected in the technology hierarchy.

    It is caused by the following list of Libraries: silterraB18V; cdsDefTechLib;

    *WARNING* (TECH-2000050): Unable to set references on tech because conflicts would result in tech silterraB18V.

    INFO (TECH-180011): Design library 'test101' successfully attached to technology library 'silterraB18V'.

Reply

  • CIW after adding technology file to the new library named "test101" p, li { white-space: pre-wrap; }

    Loading silterraB18V/libInit.il ...

    Loading silterraB18V/loadCxt.ile ... done!

    Loading context 'silterraB18V' from library 'silterraB18V' ... done!

    Loading context 'pdkUtils' from library 'silterraB18V' ... done!

    Loading silterraB18V/display.drf ...

    done!

    Loading silterraB18V/libInitCktPro.il ... done!

    Loading silterraB18V/libInitCustomExit.il ... Initializing loadCxt.ile from libInit.il for library silterraB18V...

    function PasLoadLibContext redefined

    Initializing silterraLoadSkillDir.ile from libInit.il for library silterraB18V...

    Loading oasis.cxt

    Loading analog.cxt

    Loading asimenv.cxt

    Loading spectrei.cxt

    Loading relXpert.cxt

    Loading hspiceD.cxt

    ..........................................

    . Current PDK Configuration .

    ..........................................

    . Metal Option : 6LM

    . Top Metal : Standard

    . Mim : 1FF

    . H Poly : 1K

    . MV Option : MV

    . HV Option : B18V40

    ..........................................

    . *Note* The DC current through resistors should not exceed 1mA per um of width.

    . Above this current level, the voltage coefficients may not behave properly.

    ..........................................

    done!

    Loaded silterraB18V/libInit.il successfully!

    *WARNING* (TECH-2000178): A Default Manufacturing Grid conflict has been detected in the technology hierarchy.

    It is caused by the following list of Libraries: silterraB18V; cdsDefTechLib;

    *WARNING* (TECH-2000050): Unable to set references on tech because conflicts would result in tech silterraB18V.

    INFO (TECH-180011): Design library 'test101' successfully attached to technology library 'silterraB18V'.

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