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  3. Declaring global net in schematic composer

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Declaring global net in schematic composer

RFStuff
RFStuff over 11 years ago

 Dear All,

I want to name a net as global so that it can be accessed in the hierarchy.

But also I want the same net should not be created as a PIN in layout.

Could anybody please tell how that can be achieved ?

Kind Regards,

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  • skillUser
    skillUser over 11 years ago

    Hi,

    An exclamation point after the net name indicates that it is a global net, for example "vdd!" is considered a global net. If you have a pin for this in the schematic view, when creating a layout using VLS-XL, then a pin will be created in the layout view.  Why do you not want the pin to be created in the layout?  If a connection has to be connected to or through a block then it would need to be present in the layout, no?

    regards,

    Lawrence.

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  • RFStuff
    RFStuff over 11 years ago

     When I create the net say xyz!, even if I don't create a PIN in schematic for it, the Layout automatically expects a PIN for it.

    It looks like a global net is treated as PIN/port in schematic/layout.

    If you don't label this net as a PIN in layout it creates LVS error.

    But I want this global net shouldn't be treated as a PIN/port rather it should be treated as an ordinary net .

    How that can be achieved ?

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  • Andrew Beckett
    Andrew Beckett over 11 years ago

    Not sure why that would cause an LVS error. Which LVS tool are you using?

    It's VLS XL that is creating a pin for any global net- because at the next level up you're going to need to connect to it and so that would be done using a pin rather than an internal net. There's no reason why you can't just delete the pin in VLS XL though, if you really need to. But you may then have issues using VLS XL at the level above because there's nothing to connect to in the lower level block...

    Regards,

    Andrew.

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  • pushan
    pushan over 8 years ago

    Hi,

    I also have the same requirement. Is it supported in Cadence now ?

    I need a global net (not a pin) which should be used for many cells. The issue is this net has the following requirement from LVS perspective :

    All these cells should have this net connected together but floating.

    So if it becomes a global pin, then the floating requirement is not being satisfied.

    Regards,

    Pushan

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  • Andrew Beckett
    Andrew Beckett over 8 years ago

    Is what supported in "Cadence" now (there's no tool called "Cadence", so not sure what you're referring to either)? As far as I could see from the earlier old question there wasn't anything that needed implementing in the tools - and it's not clear from your post either. Just because a net is global doesn't mean it can't be floating...

    Put simply, I don't understand what your problem is.

    Regards,

    Andrew.

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  • pushan
    pushan over 8 years ago
    Sorry for the ambiguous request.

    I am looking for this in Virtuoso Schematic Editor. Whenever I use "abc!" as wire name and use it for my cell connections, it netlists the same as Global Pin abc! and uses the same for the sub cell connections.

    I want it to not netlist it as Global Pin but still use it for the sub cells, so that though the nets are connected (same abc!) but they do not become top level Global Pin.

    Regards,
    Pushan
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  • Andrew Beckett
    Andrew Beckett over 8 years ago

    Pushan,

    Which netlister? I wouldn't have expected a global net to be netlisted as a pin of a .SUBCKT unless you made it a pin. Please give an example so it's obvious what you're talking about - I could maybe guess, but it's a guess given the information you've provided...

    Regards,

    Andrew.

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  • pushan
    pushan over 8 years ago
    Hi Andrew,

    I used CDL netlisting with Netlisting Mode as Analog.

    It is not netlisting the "abc!' as the subckt Port but it is putting the following in the CDL out which makes Calibre LVS to recognize it as a Pin :

    *.Global abc!
    *.PIN abc!

    Regards,
    Pushan
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  • Andrew Beckett
    Andrew Beckett over 8 years ago

    Finally it's clear what you were asking. There doesn't appear to be any control to stop the *.PIN from being netlisted for each *.GLOBAL net. I'm not sure why it matters -  I don't think I've seen any reports about removing this.

    The one CCR that I found was that you can use the variable simPinGlobals=t which instead of adding *.GLOBAL it will add pins through the hierarchy - although it still outputs the *.PIN at the top level. I don't know whether that's an acceptable alternative.

    Anyway, if you want different behaviour (other than manually removing the *.PIN line yourself) then you'll need to contact customer support to request control of this in the auCdl netlister, with details as to why it's needed (what goes wrong if this is there).

    Regards,

    Andrew.

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  • pushan
    pushan over 8 years ago
    Many Thanks for your help!!

    Regards,
    Pushan
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