Stats

  • Locked Locked
  • Replies 10
  • Subscribers 127
  • Views 22197
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Declaring global net in schematic composer

RFStuff

 Dear All,

I want to name a net as global so that it can be accessed in the hierarchy.

But also I want the same net should not be created as a PIN in layout.

Could anybody please tell how that can be achieved ?

Kind Regards,

Parents
  • RFStuff

     When I create the net say xyz!, even if I don't create a PIN in schematic for it, the Layout automatically expects a PIN for it.

    It looks like a global net is treated as PIN/port in schematic/layout.

    If you don't label this net as a PIN in layout it creates LVS error.

    But I want this global net shouldn't be treated as a PIN/port rather it should be treated as an ordinary net .

    How that can be achieved ?

Reply
  • RFStuff

     When I create the net say xyz!, even if I don't create a PIN in schematic for it, the Layout automatically expects a PIN for it.

    It looks like a global net is treated as PIN/port in schematic/layout.

    If you don't label this net as a PIN in layout it creates LVS error.

    But I want this global net shouldn't be treated as a PIN/port rather it should be treated as an ordinary net .

    How that can be achieved ?

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.