Problems with multiple veriloga modules but same terminal names for symbol in Spectre cell view

Dear Sir,

 I have created a symbol in Cadence Spectre Schematic tool and using 'create cellview from cellview', I added a verilog-A code for that symbol  with module name L3. And in L3module, L2 is instantiated by mentioned its file path using 'include compiler directive and instantiate syntax. And in L2 , L1 is instantiated in the same way.

L3's terminals are Source, Drain, Gate, Sub. (in symbol also i maintained only these 4 terminals only)

L2's terminals are Source , Drain, Gate, Sub, CoupleNode

L1's terminals are  Source , Drain, Gate, Sub,CoupleNode

Problems :

But when I save L3, Verilog parser says errors like port order do not match. In CIW, I get errors like this : "more than one module is there in the code" and  L3 is having 4 terminals while the other module is having 5 terminals.

So i added one dummy 5th terminal for  the symbol and I did 'netlist and run' in Virtuoso ADEL. It is running successfully but NOT getting expected output .

Kindly suggest solutions for the above problems.

Note : - Product Version 6.1.5
May 2012 (for all the software tools used for this problem)

Thanks and Regards,

K.R.Pasupathy