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GPDK045 DRC soft check error with GIOLIB045 pads

MoMiner1870

Hello all, I am trying to get our University up and running with GPDK045.  I am having problems with PVS DRC when I try to use the pads included in the GIOLIB045 library.

The details-

I have created a simple CMOS inverter layout. It passes DRC, LVS and QRC.

I then created a pad frame layout which passes DRC on its own.  The problem comes in when I place the inverter instance in the pad frame.

The Inverter has a via from M1-Psub for the ground connection of the NMOS.  This is causing Soft-Check4 and 5 errors in the pad frame.  If I remove the via, I get latch-up errors with the inverter because it does not have a tap to the substrate close enough, but the Soft-Check errors go away.

This seems like a catch 22.  Does anyone have any idea how I can get rid of these Soft-Check errors?

Thanks!

Travis Schulze

Parents
  • So I thought I had this fixed but I do not. I am still getting the Soft_Check 4 and 5 errors for my layout I have gone trough and checked all the net names on all the components and changed them all to match. I went into the NMOS and changed its grounding to match. I am still getting the errors. I am at a loss where to go from here. Is there a way to display all the net names in a design? Maybe that would help me find the mis-match.
Reply
  • So I thought I had this fixed but I do not. I am still getting the Soft_Check 4 and 5 errors for my layout I have gone trough and checked all the net names on all the components and changed them all to match. I went into the NMOS and changed its grounding to match. I am still getting the errors. I am at a loss where to go from here. Is there a way to display all the net names in a design? Maybe that would help me find the mis-match.
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