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GPDK045 DRC soft check error with GIOLIB045 pads

MoMiner1870

Hello all, I am trying to get our University up and running with GPDK045.  I am having problems with PVS DRC when I try to use the pads included in the GIOLIB045 library.

The details-

I have created a simple CMOS inverter layout. It passes DRC, LVS and QRC.

I then created a pad frame layout which passes DRC on its own.  The problem comes in when I place the inverter instance in the pad frame.

The Inverter has a via from M1-Psub for the ground connection of the NMOS.  This is causing Soft-Check4 and 5 errors in the pad frame.  If I remove the via, I get latch-up errors with the inverter because it does not have a tap to the substrate close enough, but the Soft-Check errors go away.

This seems like a catch 22.  Does anyone have any idea how I can get rid of these Soft-Check errors?

Thanks!

Travis Schulze

  • Hi Travis

    As gpdk does not has a substrate cutting layer, you need to use the same ground net in all the blocks. Would you please check if different ground nets have been used in the pad frame and inverter? E.g. pad frame uses "gnd" but inverter uses "vss", etc.

    Best regards
    Quek

  • Thanks Quek, you nailed it. I had originally named the net gnd!. But when I changed the name to vss it ran fine. Thanks again!
  • So I thought I had this fixed but I do not. I am still getting the Soft_Check 4 and 5 errors for my layout I have gone trough and checked all the net names on all the components and changed them all to match. I went into the NMOS and changed its grounding to match. I am still getting the errors. I am at a loss where to go from here. Is there a way to display all the net names in a design? Maybe that would help me find the mis-match.

  • Hi Daryl

    Would you please run a PVS LVS and check "abcde.spi" file in the PVS LVS run directory? This is the layout netlist generated by PVS. You please search through this file to find the cause of the error. E.g. search for gnd!, etc.

    I am actually a little puzzled. PVS DRC debug window should also allow you to zoom to the stamping error location if you click on the error. May I know if there are any problems in using the DRC debug window to locate the error?

    Best regards
    Quek

  • Hi, Quek thanks again for your response.  

    I know exactly where there error is. I just can't figure out how to fix it.  When I run PVS DRC I get 1 soft check 4 and 54 soft check 5 errors.

    The soft check 4 is telling me that the M1-Psub via is causing multiple ptaps to the substrate.  The 54 soft check 5 errors are all in the GIOlib pads.  The M1-Psub via is needed to prevent latchup on my inverter (which is the only circuit element in this trial design).

    I can change the net of the M1-Psub via no problem. I have tried gnd!, vss, even leaving it blank but I still get the same errors.   I think if I could see what the other ptaps  to the substrate were called that might help.  But they are in the pads.  The pads will not allow me to edit them.  I can read the properties of the various layers such as M1 where I connect up to the pad, but its connectivity is blank.


    I do not have a schematic for these pads so there is nothing to run LVS against.  Would it be beneficial to create a schematic?  If so that brings up a slew of other questions since the pad symbols have extra pins that I don't know what to do with.

    Thanks

  • Hi Daryl

    Would you please run LVS using any dummy schematic? We just need to complete the LVS run so that the LVS database can be generated.
    - After completing the run, please "Tools->Probing form" in the LVS debug window.
    - Click on "Add Probe" button and then click on the M1-Psub via that is causing the problem
    - Check the nets listed for the layers in the pop-up form
    - Are there any clues to the problems?


    Best regards
    Quek

  • Ok Quek, so I ran the probe on the M1-Psub via. the via is made up of 4 layers 3 of them are on net 7 which connects to the Vss pad as expected. the Psubstrate layer though is on net 4 which connects to every pad. Any idea how the via got onto two different nets? Or how to fix it? Thanks again!

  • Hi Daryl

    All the m1-psub taps need to be connected together. Would you please check if the m1-psub tap has already been connected to the m1-psub taps in the padframe? If you use PVS probing or Virtuoso marknet on a ptap, the ptaps in the inverter and padframe should all be highlighted.


    Best regards
    Quek

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