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GPDK045 DRC soft check error with GIOLIB045 pads

MoMiner1870

Hello all, I am trying to get our University up and running with GPDK045.  I am having problems with PVS DRC when I try to use the pads included in the GIOLIB045 library.

The details-

I have created a simple CMOS inverter layout. It passes DRC, LVS and QRC.

I then created a pad frame layout which passes DRC on its own.  The problem comes in when I place the inverter instance in the pad frame.

The Inverter has a via from M1-Psub for the ground connection of the NMOS.  This is causing Soft-Check4 and 5 errors in the pad frame.  If I remove the via, I get latch-up errors with the inverter because it does not have a tap to the substrate close enough, but the Soft-Check errors go away.

This seems like a catch 22.  Does anyone have any idea how I can get rid of these Soft-Check errors?

Thanks!

Travis Schulze

Parents

  • Hi, Quek thanks again for your response.  

    I know exactly where there error is. I just can't figure out how to fix it.  When I run PVS DRC I get 1 soft check 4 and 54 soft check 5 errors.

    The soft check 4 is telling me that the M1-Psub via is causing multiple ptaps to the substrate.  The 54 soft check 5 errors are all in the GIOlib pads.  The M1-Psub via is needed to prevent latchup on my inverter (which is the only circuit element in this trial design).

    I can change the net of the M1-Psub via no problem. I have tried gnd!, vss, even leaving it blank but I still get the same errors.   I think if I could see what the other ptaps  to the substrate were called that might help.  But they are in the pads.  The pads will not allow me to edit them.  I can read the properties of the various layers such as M1 where I connect up to the pad, but its connectivity is blank.


    I do not have a schematic for these pads so there is nothing to run LVS against.  Would it be beneficial to create a schematic?  If so that brings up a slew of other questions since the pad symbols have extra pins that I don't know what to do with.

    Thanks

Reply

  • Hi, Quek thanks again for your response.  

    I know exactly where there error is. I just can't figure out how to fix it.  When I run PVS DRC I get 1 soft check 4 and 54 soft check 5 errors.

    The soft check 4 is telling me that the M1-Psub via is causing multiple ptaps to the substrate.  The 54 soft check 5 errors are all in the GIOlib pads.  The M1-Psub via is needed to prevent latchup on my inverter (which is the only circuit element in this trial design).

    I can change the net of the M1-Psub via no problem. I have tried gnd!, vss, even leaving it blank but I still get the same errors.   I think if I could see what the other ptaps  to the substrate were called that might help.  But they are in the pads.  The pads will not allow me to edit them.  I can read the properties of the various layers such as M1 where I connect up to the pad, but its connectivity is blank.


    I do not have a schematic for these pads so there is nothing to run LVS against.  Would it be beneficial to create a schematic?  If so that brings up a slew of other questions since the pad symbols have extra pins that I don't know what to do with.

    Thanks

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